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QuickLogic introduces new Australis eFPGA IP Generator


QuickLogic, the developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP and Endpoint AI solutions, announced its new Australis embedded FPGA (eFPGA) IP Generator. This groundbreaking tool is a culmination of the company’s three decades of deep domain expertise in designing and shipping programmable logic architectures that are silicon-efficient, reliable, high quality, and manufacturable at scale, implemented using the silicon automation design techniques of the OpenFPGA open-source framework.

“With the release of Australis, we’re underscoring our commitment to and leadership in leveraging open-source tools with our deep domain expertise in programmable logic to deliver embedded FPGA technology to the market,” said Brian Faith, QuickLogic’s president and chief executive officer.

Severe semiconductor supply constraints and difficulties keeping up with Moore’s Law have driven system developers to pursue designing their own, more domain-specific devices. However, these are typically expensive, take longer to develop, and introduce risk. Integration of embedded FPGA technology is a possible solution to mitigate these risks, but historically it had to be “hand-crafted” and tied to a particular foundry and a specific process node. Australis addresses these issues by giving developers the ability to customise their eFPGA IP quickly and cost effectively.

Australis is based on the OpenFPGA IP generator and adds a multitude of additional features and capabilities specific to implementing QuickLogic’s eFPGA IP solutions, along with the level of testing and support required to build commercially viable eFPGA IP.

QuickLogic utilizes the Australis eFPGA IP Generator to provide ASIC/SoC developers an easy, highly automated way to define and implement customized eFPGA IP for their projects. Embedded FPGA flexibility enables a multitude of reprogrammable use cases – including addressing changing market conditions, supporting the evolution of new standards with the same silicon, customized implementations for intellectual property protection, offloading and hardware acceleration of artificial intelligence / machine learning workloads, or simply for creating a range of product variants for fragmented markets.

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