The recently-formed OpenHW Group launched the CORE-V Chassis project in the effort to create a heterogeneous multi-core processor evaluation system-on-a-chip (SoC) running the Linux operating system. The CORE-V Chassis will see a CV64A 64-bit core alongside a CV32E 32-bit coprocessor core, with a tape-out deadline of the latter part of 2020.
“The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP and tools. With the tape out of a functional evaluation SoC during the second half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives,” said Rick O’Connor, OpenHW Group CEO.
Based on the NXP iMX platform, the resulting CORE-V Chassis evaluation SoC will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP)DDR4, and multiple SDIO interfaces, along with a wide range of further peripheral blocks.
The 64-bit CV64A core in the CORE-V Chassis is based on the RV64GC RISC-V core IP, originally developed as part of the PULP Platform at the University of ETH Zurich. Optimised for performance, the CV64A core will be capable of clock frequencies of 1.5GHz and alongside the CV64A, is a highly capable CV32E coprocessor core based on the RV32IMFCXpulp RISC-V core IP, also from the University of ETH Zurich.
Once completed, the CORE-V Chassis is earmarked to form the basis of further multi-core evaluation SoCs.