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InGaP/GaAs HBT comparator for a 4GS/s 6-bit ADC

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By Jincan Zhang, Min Liu, Liwen Zhang, Jinchan Wang, Leiming Zhang, Henan University of Science and Technology, China

High-performance and high-speed electronic systems are in great demand a wide variety of applications. At the heart of most of these applications typically lie analogue-to-digital converters (ADCs). Of these, wide-bandwidth ADCs with high sampling rates and moderate resolution are mostly needed in applications such as digital sampling oscilloscopes, radar, satellite and broadband communication systems.

Inside an ADC

Comparators form an essential part of ADCs; not only do they represent the link between analogue and digital domains, they also play a significant role in the overall sampling rate and resolution of the ADC.

Here we present an InGaP/GaAs HBT (heterojunction bipolar transistor) comparator based on a master-slave architecture for a 4GS/s 6-bit ADC.

Figure 1: Comparator block diagram

As shown in Figure 1, the comparator consists of a preamplifier, a DFF (master-slave latch), an output buffer and a clock driver. The clock driver converts the input sine wave into track/latch control signals with low jitter.

Fig. 2 Preamplifier in the comparator

The preamplifier, as shown in Figure 2, is introduced to improve comparator sensitivity to low-level input signals. The emitter-followers before and after the differential amplifier create the necessary level shifting and reduce the kick-back noise created by switching of the latch in the follow-up stage. The preamplifier makes the input impedance of the divider 50W with R1 = 50Ω pull-up resistors.

Figure 3: Master-slave latch of the comparator

The master and slave latches (Figure 3) are major components in the comparator. At the same time, they have the opposite operation mode: when one latch is in track mode, the other is in hold mode.

With the latches placed in series, the metastability of the comparator is increased. Adding emitter followers (Q11, Q12, Q17, Q18) reduces the loading effect of the following stage and speeds up the regeneration process.

Figure 4: Output buffer of the comparator

Figure 4 shows a simple output buffer with two collector load resistors R4 of 50W, matched to the input impedance of the test instrumentation. A tail current I6 is provided to keep the moderate output amplitude.

Figure 5: Microphotograph of the comparator

Measurement

The comparator was fabricated in WIN 1µm InGaP/GaAs HBT technology; see the chip’s microphotograph in Figure 5. It occupies an area of 1mm × 0.74mm.

The schematic diagram of the on-wafer measurement system is shown in Figure 6. The clock and analogue input signals in the test were generated by Agilent E8257D and HP 83752B signal generators, respectively. The output was observed using Teledyne LeCroy’s SDA 816Zi-A real-time oscilloscope. All these signals were connected by high-frequency probes and cables.

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Figure 6: Diagram of the measurement system

The comparator was biased at VDD = 6V (IDD = 27.7mA), consuming 166.2mW of DC power. The comparator’s differential output waveform operated at a clock frequency of 15GHz, with an input frequency of 1GHz; see Figure 7. It can be seen that the comparator works well.

Operating at Nyquist frequency, the measured differential output waveform of the comparator at 4GHz sampling rate is shown in Figure 8, where the input peak-to-peak voltage is 18mVpp, equivalent to about 6 bits of ADC resolution for the full input range of 1.2Vpp.

The comparator is well-suited for the use in moderate-resolution and high-speed ADCs.

Figure 7: Measured differential output waveform with 15GHz clock and 1GHz input (x: 1ns/div, y: 50mv/div)

Figure 8: Measured differential output waveform with 4GHz clock and 2GHz input (x: 500ps/div, y: 50mv/div)

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