share article

Share on facebook
Share on twitter
Share on linkedin

Agile Analog joins RISC-V International as a strategic member


Agile Analog, a supplier of highly-configurable process node-agnostic analogue IP building blocks, has joined the RISC-V International non-profit organisation to widen access to its application- and process-optimised analogue IP. RISC-V International maintains RISC-V as a free and open processor instruction set architecture (ISA).  

Increasing numbers of OEMs and manufacturers of SoCs and ASICs are choosing to base complex chip designs on the RISC-V architecture, as its open licence business model enables them to develop chip designs faster and to enjoy greater design flexibility than is possible when using proprietary processor architectures.

John Hartley, Chief Commercial Officer at Agile Analogy, said, “RISC-V International maintains the largest and most vibrant ecosystem of tools and IP in the industry, so Agile Analog is delighted that its unique ability to optimise analog IP for any application and process has been recognised by the award of strategic member status.”

Demand is particularly strong in new RISC-V-based chip designs for security monitoring functions, such as clock glitch and voltage glitch detection, which are used to protect against side-channel attacks. Agile Analog’s configurable IP is also available to support a wide range of other analogue functions including power management, sensing and signal processing.

“‘Having an extensive ecosystem of hardware and software IP is critical as RISC-V members continue to look for new ways to innovate from the IoT to HPC, AI, automotive and beyond,’ said Calista Redmond, CEO of RISC-V International. ‘Agile Analog’s customisable analog IP will give the RISC-V community even more options to push the boundaries of design with RISC-V,” said Hartley.

The Agile Analog offering complements the open RISC-V ISA, as its analog IP can be configured to meet the functional requirements of each application, as well as the foundry, process and node in which the chip is to be fabricated. Just as chip designers have the freedom to optimise their implementation of the RISC-V ISA, Agile Analog also enables them to choose the configuration options for analog IP. The provision of application- and process-optimised analog IP is a unique capability of Agile Analog, and is in marked contrast to the existing business model for the supply of analog IP, which is limited to the provision of off-the-shelf, standard IP products.

Share this article

Share on facebook
Share on twitter
Share on linkedin

Related Posts

View Latest Magazine

Subscribe today

Member Login