JTAGLive (by JTAG Technologies) announces the introduction of a new series of hardware debug tools for DSP and microprocessor systems utilising RISC and DSP cores. With JTAGLive CoreCommander engineers can now activate the OCD (On-Chip Debug) modes of a range of popular cores interactively to effect ‘kernel-centric’ testing of their designs.
While many devices are now equipped with a JTAG (IEEE Std. 1149.1) boundary-scan test registers (BSR) to provide test access into digital and mixed-signal designs, a significant number of microprocessors and DSPs can be found with deficient or even non-existent boundary-scan test registers. For the electronics engineer this can at-best be considered ‘frustrating’ as they look to employ alternative methods for testing the ‘processor and/or associated cluster/peripheral components.
CoreCommander routines are ideal for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair as no on-board code is required to set-up memory reads and writes from the device core. What’s more since CoreCommander routines are supplied with a Python ‘wrapper’ they complement perfectly JTAG Technologies Python-based Script product providing access to analogue elements such as ADCs and DACs and synchronised testing to full boundary-scan devices – ideal in production.
Supported cores include ARM 7/9/11, Cortex M3, PowerPC, TriCore and C2xxx.