X-FAB and Cadence have created a joint solution that allows customers to transition their designs quickly and efficiently between technologies. It combines X-FAB’s PDKs and Cadence’s Virtuoso Studio design migration technology.
As today’s CMOS technologies continue to evolve, identifying an effective design migration path has become an urgent requirement. The need to move existing IP to smaller, more advanced geometries is increasingly driven by demands for higher performance, lower power consumption, and reduced silicon area. Semiconductor developers must reverify, adjust, or redesign to ensure functionality is preserved without compromising the benefits of the target node. Adopting fast, reliable, and cost-effective migration strategies is also essential to maintaining product lifecycles and meeting market commitments, while simultaneously unlocking the gains of advanced process technologies.
“Design migration is becoming a strategic priority for semiconductor companies navigating technology evolution, supply chain issues, and geopolitical challenges,” said Ashutosh Mauskar, Corporate Vice President of Custom Products Group at Cadence.
Through the partners’ collaboration, X-FAB customers gain access to a proven migration methodology supported by Cadence Virtuoso Studio, a next-generation tool that brings a new level of automation for custom IC design and layout migration. The solution enables a rapid and straightforward path between technology nodes, supported by built-in optimization capabilities that help achieve right-first-time results. A successful proof of concept has already demonstrated migration from 180 nm to 110 nm, with the broader offer supporting a range from 1 µm to 110 nm.
A key element of the joint approach is tight integration between the Cadence migration environment and X-FAB’s PDKs. While Cadence provides the design migration framework and circuit re-optimisation tools, X-FAB contributes deep process knowledge and device mapping expertise. Customers receive dedicated mapping files to enable accurate translation of devices between technologies, significantly reducing complexity while preserving critical performance parameters.
