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Vision-Based System Design Part 11 – Securing Embedded Vision Systems against Malicious Attackers


For this reason, many industrial, security and automotive applications use uncooled image sensors like the FLIR Lepton.
Creating an uncooled thermal imager presents a range of challenges for embedded vision designers, requiring a flexible interfacing capability to interface with the select device and display, while providing the processing capability to implement any additional image processing upon on the video stream. Of course, as many of these devices are hand held or power constrained, power efficiency also becomes a significant driver.

Example Architecture
The FLIR Lepton is a thermal imager which operates in the long wave IR spectrum, it is a self-contained camera module with a resolution of 80 by 60 pixels (Lepton 2) or 160 by 120 pixels (Lepton 3). Configuration of the Lepton is performed by an I2C bus while the video is output over SPI using a Video over SPI (VoSPI) protocol. These interfaces make it ideal for use in many embedded systems which require the ability to image in the IR region.
One example combines the Lepton with a Xilinx Zynq Z7007S device mounted on a MiniZed development board. As the MiniZed board supports WiFi and Bluetooth it is possible to create both IIoT / IoT applications and traditional imaging solutions with a local display, in this case a 7-inch touch display. This example will create a design which interfaces with the FLIR Lepton and outputs the video on a local display.
To create a tightly integrated solution, designers can use the processing system (PS) of the All Programmable Zynq SoC to configure the Lepton using the I2C bus. The PS can also provide an interface to the radio module for WiFi and Bluetooth communications for future upgrades, which add wireless connectivity, while the programmable logic is used to receive VoSPI, perform direct memory access with DDR and output video for a local display. The high-level architecture of the solution is demonstrated within figure 2.

Within the image processing pipeline, designers can instantiate custom image processing functions generated using High Level Synthesis or use pre-existing IP blocks such as the Image Enhancement core which provides noise filtering, edge enhancement and halo suppression.
This high-level architecture requires translation into a detailed design within Vivado, as such the following IP blocks are used to create the hardware solution.
• Quad SPI Core – Configured for single mode operation, receives the VoSPI from the Lepton.
• Video Timing Controller – Generates the video timing signals for the output display.
• VDMA – Reads an image from the PS DDR into a PL AXI Stream.
• AXI Stream to Video Out – Converts the AXI Streamed video data to parallel video with timing syncs provided by the Video Timing Core.
• Zed_ALI3_Controller – Display controller for the 7-inch touch screen display.
• Wireless Manager – Provides interfaces to the Radio Module for Bluetooth and WiFi. While not used in this example, including this module within the HW design means addition of wireless communications requires only additional SW development.
When these IP blocks are combined with the Zynq processing system and the necessary AXI interconnect IP, developers obtain a detailed hardware design.

Software Definition
Most of the IP blocks included within the Vivado design require configuration using application software developed within SDK. This provides the flexibility to change the operational parameters required as the product evolves, for example accommodating a larger display or changing sensor from the Lepton 2 to the Lepton 3. For this example, no operating system is required, the application software configures the video timing from the video timing controller (800 pixels by 480 Lines), along with configuring the video direct memory access controller, to read frames from the memory mapped DDR and convert it into an AXI Stream to be compatible with the image processing stream.

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