To create a tightly integrated solution, designers can use the processing system (PS) of the All Programmable Zynq SoC to configure the Lepton using the I2C bus. The PS can also provide an interface to the radio module for WiFi and Bluetooth communications for future upgrades, which add wireless connectivity, while the programmable logic is used to receive VoSPI, perform direct memory access with DDR and output video for a local display. The high-level architecture of the solution is demonstrated within figure 2.
Within the image processing pipeline, designers can instantiate custom image processing functions generated using High Level Synthesis or use pre-existing IP blocks such as the Image Enhancement core which provides noise filtering, edge enhancement and halo suppression.
This high-level architecture requires translation into a detailed design within Vivado, as such the following IP blocks are used to create the hardware solution.
• Quad SPI Core – Configured for single mode operation, receives the VoSPI from the Lepton.
• Video Timing Controller – Generates the video timing signals for the output display.
• VDMA – Reads an image from the PS DDR into a PL AXI Stream.
• AXI Stream to Video Out – Converts the AXI Streamed video data to parallel video with timing syncs provided by the Video Timing Core.
• Zed_ALI3_Controller – Display controller for the 7-inch touch screen display.
• Wireless Manager – Provides interfaces to the Radio Module for Bluetooth and WiFi. While not used in this example, including this module within the HW design means addition of wireless communications requires only additional SW development.
When these IP blocks are combined with the Zynq processing system and the necessary AXI interconnect IP, developers obtain a detailed hardware design as shown in figure 3.
Software Definition
Most of the IP blocks included within the Vivado design require configuration using application software developed within SDK. This provides the flexibility to change the operational parameters required as the product evolves, for example accommodating a larger display or changing sensor from the Lepton 2 to the Lepton 3. For this example, no operating system is required, the application software configures the video timing from the video timing controller (800 pixels by 480 Lines), along with configuring the video direct memory access controller, to read frames from the memory mapped DDR and convert it into an AXI Stream to be compatible with the image processing stream.
Following the initialisation of the IP blocks the applications software performs the following:
• Configures the FLIR Lepton to perform automatic gain control.
• Synchronises with the VoSPI data to detect the start of a valid frame.
• Applies a Digital Zoom to scale up the image to utilise efficiently the 800 pixels by 480-line display. This can be achieved by outputting each pixel either 8 or 4 times depending upon the sensor selection.
• Transfers the frame to the DDR Memory. As the FLIR Lepton only outputs 8-bit data when ACG is enabled, this is mapped to the green channel of the RGB display.
When the completed programme is executed on the MiniZed with the FLIR Lepton connected and outputting to a 7-inch touch sensitive display, the output of the FLIR can be seen very clearly.
Wrapping Up
Imaging outside the visible range provides significant benefits and is used across several applications, although each application requires careful selection of the sensor technology. This article has demonstrated how an uncooled thermal imaging solution can be quickly and easily created using a cost-optimised Zynq SoC designed with Xilinx IP cores.
You can find the reference design here
For more information, please visit: http://www.xilinx.com/products/design-tools/embedded-vision-zone.html
