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Understanding the 3-D geometry of a tri-gate transistor and how it can improve FPGA performance

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Altera® has recently announced their Generation 10 family of FPGA devices.  This new breed of FPGAs uses the 3-D geometry and structure of the Intel Tri-Gate transistor. The Tri-Gate (also known as FinFET) technology provides a host of important improvements over the historic planar transistor structure, all related to the three sided ‘wrap-around’ effect of the MOSFET gate around the source-to-drain ‘channel’, hence Tri-Gate. These advantages manifest in improved performance, reduced active and leakage power, transistor design density, and a reduction in transistor susceptibility to charged particle single event upsets (SEU).  See Figure 1.

 

Figure 1 – Effective channel widths of planar and tri-gate transistor structures

 

The key performance advantage of Tri-Gate transistor architecture over traditional planar transistors can be found in the effective width of the conducting channel. The current drive capability and performance of a transistor is directly proportional to its effective channel width. The effective channel width can be significantly enhanced in a 3-D transistor structure relative to a planar transistor because of the ability to extend the width in the third dimension without any impact on the layout area as shown in

Figure 1. This provides the potential for both enhanced design flexibility for the designer of the transistor, as well as increased performance without the same penalties in 2D area that exist when enhancing channel width in a planar transistor.

 

The power advantage results from the improved control of the channel by the gate’s electric field on three sides of the fin. This reduces the subthreshold leakage current from source to drain in the ‘off state as compared to a planar transistor. In addition, the power supply voltage can be significantly reduced with Tri-Gate transistors while maintaining superior speed due to the increased effective width compared to a planar transistor. The combination of lower supply voltage and reduced leakage current results in substantial power savings. See Figure 2.

 Figure 2 – Tri-gate transistor structures provide steeper voltage curves

 Each new generation of silicon manufacturing technology generally involves a geometry shrink, or reduction in overall gate and transistor structure, that results in higher density and more capable silicon. The 3-D Tri-Gate structure itself also accommodates higher density transistor designs by extending the transistor width characteristic into the third dimension. This allows designers the ability to trade off the size and width of the transistor ‘fin’ based on performance, power, and transistor density packing objectives. In the case of Altera’s move to 14 nm TriGate design, Altera will benefit from both the transistor geometry shrink to 14 nm, and from further density improvements allowed by TriGate transistor design.

 

The SEU advantage results from the small cross-sectional area connecting the fin to the substrate in the Tri-Gate structure. This creates a smaller cross-sectional area over which charge generated by ionizing particles can be collected than in a planar transistor. The reduced susceptibility to charged particles causing bitflips in 3-D transistor-based circuits is supported by early testing on Intel’s 22 nm implementation of TriGate transistors in their products.

 

The substantial advantages of Tri-Gate silicon technologies will allow Altera to deliver previously unimaginable performance in FPGA and SoC products. This will include a historic doubling of core performance as compared to other high-end FPGAs, bringing FPGAs to the gigahertz performance level. Overall active and static power numbers will reduce by 70 percent through a combination of process, architecture, and software advances.

 

Altera users can begin designs today that take advantage of the significant performance and power efficiency benefits of TriGate technology in FPGAs. This is possible by beginning designs with the Arria®10 portfolio of 20 nm FPGA devices. Users can then take advantage of pin-forpin design migration pathways from Arria 10 FPGA and SoC products to Stratix® 10 FPGA and SoC products as they become available.

 

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