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Ultra-wideband calibration-free 6-bit 4GSps folding-interpolating ADC


By Xiangmin Li and Zhuang Kang, Yangtze University College of Arts and Sciences, and Liang Jia, University of Electronic Science and Technology, China

In high-speed optical communication receivers, high-speed analogue-to-digital converters (ADCs) provide sample information for use with DSP-based signal equalisation. High-speed ADCs are also needed for spectral identification of high-speed signals and can provide the interface to an on-chip Fast Fourier Transform (FFT) engine. But, to improve the performance of such systems, high sampling rate and medium-resolution ADCs are being pursued.

Ultra-Wideband ADCs

Ultra-wideband ADCs are required in a wide range of receiver applications, including digital radar receivers (DRRs) and ultra-wide bandwidth (UWB) communication. Figure 1 shows an example DDR system, where the antenna signal is directly digitised for further processing, after its conditioning. It can be employed in military surveillance, airborne early warning and target recognition. In these situations, low latency and no idle time for calibration are required of the ADC’s analogue core. In some high-speed ADC designs with GHz sampling frequency, there’s need for large latency because of the architecture’s multiple pipeline stages. Dedicated time for calibration is necessary, since the CMOS technology’s matching properties are poor.

In addition to wide instantaneous bandwidth, accommodating high intermediate frequencies (IF) offers significant system advantages by reducing or eliminating costly RF down-conversion circuitry. Existing silicon-based designs with resolution higher than 6-bit and 1.33GSps sample rate use flash memory for high-speed operation. However, these designs do not successfully sustain their baseband effective number of bits (ENOB) performance at input frequencies higher than the sampling rate.

Here, we describe a calibration-free 6-bit 4GSps folding-interpolating monolithic ADC, fabricated in advanced SiGe BiCMOS technology. We use the folding-interpolating architecture because it consumes less power and occupies less space than its flash counterpart while sacrificing less speed and latency.

The matching properties of hetero-junction bipolar transistors (HBTs) are about ten times better than that of metal oxide semiconductor field effect transistors (MOSFETs). By using an on-chip highly-linear track-and-hold amplifier (THA), the architecture can sample input frequencies up to 5.5GHz with 5.45 ENOB performance, which is close to the ideal value of 6….

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