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Totem-pole PFC techniques and technologies for more efficient PSUs

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By Yong Ang, Yong Ang, Strategic Marketing Director, ON Semiconductor

Losses in an input bridge rectifier are a hurdle in achieving the best efficiency from AC-DC power supplies. The bridgeless totem-pole power factor correction (PFC) is an elegant solution that replaces the lossy bridge rectifier and PFC FET and boost diode with four active switching devices. However, the topology must use a complex control algorithm and this may need a microcontroller, which can be expensive. The cost and complexity of the control element presents a barrier to adoption of the technique for some engineering teams.

Ubiquitous

AC-DC power supplies are ubiquitous, accounting for a large proportion of global energy draw, so their efficiency affects system cost and emissions it contributes. When discussing AC-DC power, there is another, very important parameter – input power factor. If the line current and line voltage do not have the same sinusoidal waveshape and phase, the apparent power drawn by the supply is higher than necessary. This results in inefficiencies propagating back through the utility network. This inefficiency can be addressed through PFC, which has now become a statutory requirement in a number of countries and regions. A typical power supply unit (PSU) without active power factor correction can easily draw 70% more current than one with correction, which is why it is now mandatory to incorporate circuitry to correct power factor to a value close to unity.

More correctly, EMC standards such as IEC 61000-3-2 place limits on the power in line harmonics, up to the 40th, generated by the distorted line current. The 80 Plus certification program promotes 80% efficiency, which relates to efficiency at 20%, 50% and 100% loading. The highest level of 80 PLUS standard is known as ‘80+ Titanium standard’, which specifies at least 90% efficiency from 10% loading up to 100%.

80+ Titanium standard

The traditional way to actively correct power factor is to use a boost converter from rectified mains to a DC level higher than the mains voltage peak, see Figure 1 (left). Pulse-width modulation is employed to regulate the DC level and simultaneously force the line current to follow the line voltage waveform.

The technique works well and is easy to control in continuous, discontinuous and critical conduction modes, relating to whether the boost inductor energy is fully exhausted each cycle or not. However, there is also pressure to increase AC-DC converter efficiency, with the strictest ‘80+ Titanium standard’ level for servers mandating up to 96% efficiency at 230VAC input at 50% load. Typically, 2% loss is allowed for the DC-DC stage leaving just 2% for the line rectification and PFC stage, but more than 1% is easily lost in the bridge rectifier alone and up to around 1.7% at low line.

Figure 1: Traditional (left) and (right) bridgeless totem-pole PFC circuits

A more-efficient technique has therefore been developed, the bridgeless Totem Pole PFC, or TPPFC, (Figure 1, right), in which the boost diode is replaced by a synchronous rectifier, enabling the boost transistor and boost diode, Q1 and Q2, to swap functions, depending on mains polarity. Now only two line-rectifier diodes are necessary, and they can also be synchronous rectifiers Q3 and Q4 as shown, for even better efficiency.

With perfect switches, an ideal inductor and no diode voltage drops, the efficiency of the TPPFC circuit can approach 100%. However, real switches have conduction and switching losses and, although ultra-low on-resistance MOSFETs can be used (even paralleled) to achieve low conduction losses, this invariably increases dynamic losses, which means a balance must be struck.

Dynamic losses stem from reverse recovery of the MOSFET configured as the boost synchronous rectifier, when its body diode conducts in the switching ‘dead’ time and also from charge and discharge of the switch output capacitance. The effect on efficiency can be so severe that silicon MOSFETs, even the ‘superjunction’ types are not viable to use in the circuit when operating in continuous-conduction mode. Consequently, wide band gap switches in silicon carbide and gallium nitride have to be considered.

Continuous conduction mode (CCM) is favoured at higher power because peak switch and inductor currents can be set low, reducing rms values and keeping conduction and inductor core losses low. This is a ‘hard’ switching mode however, with the reverse recovery and output capacitance effects causing high dynamic losses.

At low powers, discontinuous conduction mode (DCM) has low turn-on losses, as at this point boost diode current has fallen to zero and there is therefore no charge to recover. However peak and rms currents can be unmanageable causing high ohmic and core losses, so the mode is unsuitable for high power.

A compromise

A good compromise, useable up to a few hundred watts or higher with interleaving, is to operate in critical conduction mode, or CrM. In this mode, switching frequency is varied to force the circuit to operate on the border between CCM and DCM as load current or line voltage changes. The benefits of low turn-on loss are retained while limiting the peak current to 2x average for reasonable conduction and core loss; see Figure 2.

Figure 2: PFC boost inductor current waveform, critical conduction mode

Turn-off in CrM though produces hard switching commutation, with any forward recovery of the boost diode causing some loss and output voltage overshoot. The CrM’s variable switching frequency also does have the disadvantage that, at light load, frequency can be very high, producing more switching losses and degraded efficiency. The relationship is given by:

The equation would imply a direct inverse relationship of switching frequency to input power; a 20% to 100% load power or 5x change should produce a 5x change in frequency for constant efficiency. However, higher frequency reduces efficiency anyway, so the factors interact. The relationship between frequency and rms line voltage is more complex, producing typically more than 2:1 variation in frequency over the line range, peaking at mid-voltage.

Reducing light load losses

The drop in efficiency can be up to 10% at light load and is a real problem when trying to meet standby or no-load energy consumption limits. A solution to the problem is to clamp or ‘fold-back’ the maximum frequency allowed, by forcing the circuit into DCM at light loads, where the higher peak currents compared with CrM are already at a lower level.

So, a good solution for PFC technique at medium loads and high efficiency, across the line and load range, is the totem-pole arrangement with frequency clamping. The circuit should use a combination of silicon MOSFETs for AC line synchronous rectification and wide band gap switches for the high-frequency ‘leg’. Controlling this circuit is a challenge however, with four active devices to be driven, detection of zero diode current to force CrM, automatic crossover to DCM at light load, while at the same time regulating output voltage and maintaining high power factor. Switch overcurrent protection is desirable, as is output over-voltage detection. All this can be realised by implementing the complex control algorithms in a microcontroller, interfaced to the switches and sensed parameters. However, the solution can be expensive and the power designer must now get involved in coding the device for optimum performance – a daunting and time-consuming task for those unfamiliar.

TPPFC CrM controller

A simpler solution is now offered by ON Semiconductor, requiring no coding. The NCP1680 is believed to be the industry’s only mixed-signal CrM TTPFC controller, offered in a SOIC-16 package. The device has a proprietary low-loss current sensing architecture and proven control algorithms for a cost-effective, low-risk but high-performance solution. The part features constant on-time CrM and ‘valley switching’ during frequency foldback at light loads to enhance efficiency by switching at a voltage minimum. The digital voltage control loop is internally compensated for ease of system design with optimised performance across the load range. Cycle-by-cycle current limiting is included for protection, without the need for a Hall-effect sensor. A simplified schematic showing the implementation of a totem-pole PFC stage using the NCP1680 is shown in Figure 3.

Figure 3: Simplified typical TPPFC application diagram using NCP1680

An evaluation board for the NCP1680 is also available (Figure 4), which uses GaN HEMT cells for the fast switches and Si-MOSFETs for the AC line synchronous rectifiers. It provides 300W at 395VDC from 90-265VAC line and shows full load efficiency peaking at close to 99% with 98% achieved across the line range, down to 20% load; see Figure 5.

Figure 4: ON Semiconductor NCP1680 evaluation board

Figure 5: Efficiency plots of the ON Semiconductor NCP1680 evaluation board

With the availability of wide-bandgap semiconductors and a cost-effective mixed signal, critical conduction mode controller from ON Semiconductor, the totem-pole PFC stage becomes an ideal solution for high-efficiency power factor correction to several hundred watts whilst enabling compliance with the 80+ Titanium efficiency standard and eco-design requirements for standby and no-load losses.

With demand for higher efficiency coming from every vertical sector, the improvement in active PFC that can be achieved using CrM to reduce losses at all load levels will be welcomed by manufacturers, consumers and utility service providers. Engineers can start evaluating the NCP1680 now and bring higher levels of efficiency to new product development, in all application areas.

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