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Thorough Pre-Silicon Verification of Automotive SoCs

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By Richard Pugh, Product Marketing Manager, Siemens Digital Industries Software

The advent of electrified and autonomous vehicles has enormous implications for the semiconductor market. The electrification of vehicles, which addresses the need for better fuel economy and lower levels of noxious emissions, drives increased silicon content. Beyond this, electrified and autonomous vehicles must be safe as dictated by the ISO 26262 standard. The risk of injury or death raises the stakes and expectations for components, subsystems and systems within the vehicle. This drives the need for far more thorough verification of every aspect of a vehicle, particularly those that affect safety-critical functions. More silicon will be needed, much of which will require a higher degree of verification.

The new silicon content will be far more complex than previous small islands of electronics in simple ECUs. Instead, it will involve system-on-chip (SoCs) with functions specifically geared toward vehicles. Such SoCs will act as platforms that allow Tier 1 suppliers and OEMs to differentiate and add value through the selection of silicon features and the use of software that runs on the SoCs.

This further complicates SoC verification. A SoC isn’t truly complete until software runs on it. Whilst a semiconductor company can’t thoroughly check the software that a Tier 1 supplier writes, it can ensure that the lowest-level software – drivers, which provide the higher-level software with access to the silicon – operates correctly as it interacts with a selected operating system (OS). No SoC can be said to have been thoroughly verified until it has been exercised with an OS and driver executing higher-level test code.

Automotive SoC verification

Specific verification challenges include:

  • SoCs will be large and complex, with multiple CPUs, artificial intelligence (AI) capabilities and vision-oriented features.
  • Extensive low-level software will need to be checked out.
  • Battery-operated electrified vehicles mean that SoCs must consume energy judiciously, and the power characteristics must be verified.
  • Numerous interfaces and protocols involving hardware and software will need to be verified.
  • These SoCs will be large enough that, done poorly, verification would take far too long to allow commercial relevance.

Figure 1: Automotive SoCs are large and complex with multiple CPUs, AI capabilities, and vision-oriented features, along with interfaces and protocols that need to be verified

The chosen verification strategy must be able to accommodate huge circuits running an OS and millions of lines of code. While a semiconductor company may verify the lower-level code, the verification methodology and model should be transferable to a Tier-1 supplier for integration into a larger system so that they can verify the higher-level software that it will create.

The older standard automotive flow leverages four tools for ensuring that systems operate correctly:

  • Virtual prototypes: these make use of high-level models of hardware behaviour prior to silicon availability. The models execute quickly, but their accuracy is insufficient for full verification.
  • Hardware-in-the-loop (HIL): this is an option after hardware becomes available and is stable. This approach relies on existing hardware rather than a fully instrumented verification testbench, and as a result verification stimulus is non-deterministic and observability may be limited. This makes it extremely difficult to debug any issues. It may be useful for a quick checkout of newly-built integrated circuits, but it’s insufficient for thorough verification.
  • Software simulation: this gives full cycle accuracy prior to silicon availability, with excellent debug capabilities. It runs far too slowly for full verification coverage of SoC hardware and software. Booting an OS and testing software involves billions of cycles of execution, which is much more than a simulator can manage in a reasonable timeframe.
  • Hardware prototyping: whilst available before a chip has been manufactured, this approach lacks the capacity, debug visibility and design-change turnaround time necessary for full-chip verification.

Verification complexity is further burdened by the high cost of silicon mask sets. Whilst the prior approaches applied before and after silicon availability may accomplish much of the checkout, any hardware bugs encountered can mean enormous delays and extra costs if a silicon re-spin becomes necessary.

None of the traditional verification approaches available before silicon is sufficient due to several factors, such as lack of accuracy, limited debug, insufficient verification performance to deliver results in time for market, or being unable to provide the quality of results needed for such safety-critical applications. This leaves a pre-silicon verification gap. With the tools above, it is not possible to do a complete verification job before generating the first silicon masks.

Figure 2: Critical to success in the automotive realm is full verification that must be completed before chips are produced

Emulation closes the gap

Emulation is the only methodology available for a thorough verification program that can complete fast enough to ensure production of a competitive SoC. Veloce emulators from Mentor, for example, provide not only full-chip verification, but also a connection to the higher-level suppliers that will integrate the SoC into systems and systems-of-systems.

Silicon engineers who built SoCs in the past will be familiar with emulation, but it may be a new tool for engineers that have previously designed more limited automotive electronics. An emulator is a special-purpose supercomputer that models integrated circuits before they’re built.

  • It can run 100-10,000 times faster than software simulation can because the models are implemented in hardware.
  • It can handle as many as 15 billion gates of logic.
  • It is a full-on computing environment with its own computing hardware, operating system and software applications dedicated to simplifying specific verification tasks.
  • Emulators can be housed in data centres, making them globally available through a network connection.
  • Emulators are new to the automotive industry, but they have proven their value in verifying complex SoCs for the telecommunications, storage and mobile markets for many years. They are a well-established verification tool.

Because an emulator has such high performance, it can run extensive test suites for both hardware and software. Its ability to test out software on hardware is a central reason for its success in markets that have long had to verify software on complicated SoCs. The automotive industry now joins that set of markets, making emulation a mandatory automotive verification tool.

Emulators can be connected to virtualised data sources for test stimulus. This makes test data deterministic and repeatable, unlike real-world data sources. Debug of issues, as well as the fixes needed to resolve those issues, can proceed much more quickly.

Emulation is also about much more than just logic functionality. Numerous other automotive issues can be addressed using the applications that run on the emulator, including:

  • Verifying that power remains within budget through the SoC’s various modes.
  • Verifying and document the safety aspects of a SoC, in accordance with the ISO 26262 safety standard.
  • Silicon chips have internal test infrastructure (design-for-test, or DfT); emulation can be used to verify those circuits.
  • All of these and other verification tasks contribute to the full verification coverage. Emulators can help track and report that coverage.

Figure 3: Emulation provides full-chip verification

Applications that perform these tasks help by abstracting the implementation specifics of the tests, making verification engineers more productive.

Emulators are part of Siemens’s higher-level automotive program called PAVE360 that brings together the many tools necessary for validating all of the electrical, electronic and mechanical elements of a vehicle. Whilst the Veloce emulator has a focus on silicon, the models and testbenches can be used for higher-level system and system-of-systems verification.

That means that a SoC can be confirmed to operate correctly, not only by a semiconductor provider in the context of its own testbench, but also by Tier-1 suppliers in the context of an entire vehicle subsystem, providing much greater confidence when generating masks.

Applications that perform these tasks help by abstracting the implementation specifics of the tests, making verification engineers more productive.

Emulators are part of Siemens’s higher-level automotive program called PAVE360 that brings together the many tools necessary for validating all of the electrical, electronic and mechanical elements of a vehicle. Whilst the Veloce emulator has a focus on silicon, the models and testbenches can be used for higher-level system and system-of-systems verification.

That means that a SoC can be confirmed to operate correctly, not only by a semiconductor provider in the context of its own testbench, but also by Tier-1 suppliers in the context of an entire vehicle subsystem, providing much greater confidence when generating masks.

As automotive electronics increasingly pervade every corner of a vehicle, emulators will be there to verify those systems and components with the performance and capacity to handle the largest imaginable SoCs for many years.

Figure 4: One automotive program brings together tools necessary for validating all electrical, electronic and mechanical elements of a vehicle so an SoC can be confirmed to operate correctly in the context of an entire vehicle subsystem

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