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The emergence and growing importance of the JESD204 converter interface standard

Series

By Jonathan Harris, Applications Engineer, Analog Devices

As the resolution and speed of converters increases, the demand for a more efficient interface grows. Now, a new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. The JESD204 interface brings this efficiency and offers several advantages over its complementary metal oxide semiconductor (CMOS) and low voltage differential signaling (LVDS) predecessors in terms of speed, size and cost.

JESD204 was originally rolled out several years ago but has undergone revisions that are making it a much more attractive and efficient converter interface. The standard applies to both analogue-to-digital converters (ADCs), as well as digital-to-analogue converters (DACs), and is primarily intended as a common interface to FPGAs – but can be used with ASICs, too.

Designs employing JESD204 benefit from a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count that leads to smaller package sizes and a lower number of trace routes that make designing boards easier and cheaper. The standard is also easily scaleable.

As the standard has been adopted by an increasing number of converter vendors and users, as well as FPGA manufacturers, it has been refined and new features have been added that have increased efficiency and ease of implementation. To date, the standard has seen two revisions since its introduction in April 2006, and now stands at Revision B.

What is JESD204?

The JESD204 standard describes a multigigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. In the original, 2006, version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver; see Figure 1.

The lane shown is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnects utilising current mode logic (CML) drivers and receivers. The link shown is the serialised data link established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

Figure 1: The original JESD204 standard, introduced in 2006

Lane data rate is between 312.5Mbps and 3.125Gbps, with both source and load impedance defined as 100Ω ±20%. The differential voltage level is defined to nominally be 800mV peak-to-peak with a common-mode voltage level range from 0.72V to 1.23V. The link uses 8b/10b encoding that incorporates an embedded clock, removing the necessity for routing an additional clock line and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.

As the JESD204 standard started gaining in popularity, it became obvious that it also needed to support multiple aligned serial lanes with multiple converters, to accommodate increased converter speeds and resolutions. This led to the first revision of the JESD204 standard, which became known as JESD204A; see Figure 2. The lane data rates remained unchanged, as did the frame clock and the electrical interface specifications. Supporting multiple aligned serial lanes allowed converters to meet the maximum supported data rate of 3.125Gbps.

Figure 2: First revision – JESD204A

Although both the original JESD204 standard and the revised JESD204A were higher performance than legacy interfaces, they still lacked a key element – deterministic latency of the link’s serialised data.

When dealing with a converter, it is important to know the timing relationship between the sampled signal and its digital representation, in order to properly recreate the sampled signal in the analogue domain. This timing relationship is affected by the converter’s latency, which for an ADC is defined as the number of clock cycles between the instant of the sampling edge of the input signal until the time its digital representation shows at the converter’s outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC and the time the analogue output begins changing. In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialised digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.

Revision number 2 – JESD204B

In July 2011, the second and current revision of the standard, JESD204B, was released; see Figure 3. One of its key components was the provisions for deterministic latency. In addition, supported data rates were pushed to 12.5Gbps, broken down into different speed grades of devices. The revision also called for a transition from using the frame clock as main clock source to using the device clock as main clock source.

Figure 3: Second (current) revision – JESD204B

The JESD204B revision provides a mechanism to ensure that from one power-up cycle to the next, and across link resynchronisation events, the latency is repeatable and deterministic. One way to accomplish this is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well-defined moment by using an input signal called SYNC~. Another implementation is to use the SYSREF signal, which acts as a master timing reference, aligning all internal dividers from device clocks and local multiframe clocks in each transmitter and receiver, ensuring deterministic latency through the entire system. This is a newly-defined signal for JESD204B.

There are three device subclasses in the JESD204B specification:

  • Subclass 0 – no support for deterministic latency;
  • Subclass 1 – deterministic latency using SYSREF; and
  • Subclass 2- deterministic latency using SYNC~.

Subclass 0, in effect, is a JESD204A link. Subclass 1 is primarily intended for converters operating at and above 500MSPS, and Subclass 2 is primarily for converters operating below 500MSPS.

The JESD204B version also groups devices into three different speed grades – the source and load impedance is the same for all three speed grades being defined as 100Ω ±20%. The first speed grade aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125Gbps. The second speed grade defines the electrical interface for lane data rates to 6.375Gbps, with the minimum differential voltage level being lower at 400mV peak-to-peak, from the 500mV peak-to-peak for the first speed grade. The third speed grade defines the electrical interface for lane data rates to 12.5Gbps, with the minimum differential voltage level required for the electrical interface to 360mV peak-to-peak. As the lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.

Why is JESD204 important?

In much the same way as LVDS began overtaking CMOS as the technology of choice for the converter digital interface several years ago, JESD204 is poised to tread a similar path in the next few years. While CMOS technology is still available today, it has mostly overtaken by LVDS. The speed and resolution of converters as well as the need for lower power eventually renders CMOS and LVDS inadequate for converters. As the data rate increases on the CMOS outputs, the transient currents also increase, resulting in higher power consumption. While the current and, thus, power consumption remain relatively flat for LVDS, the interface has an upper speed bound that it can support, due to the driver architecture and the numerous data lines that must be synchronised to a data clock.

Figure 4 shows the different power consumption requirements of CMOS, LVDS and CML outputs for a dual 14-bit ADC.

Figure 4: CMOS, LVDS, and CML driver power comparison

At approximately 150-200MSPS and 14 bits of resolution, CML output drivers consume less power. CML offers the advantage of requiring fewer output pairs per given resolution than LVDS and CMOS drivers because of the serialisation of data. The CML drivers specified for the JESD204B interface have an additional advantage since the specification calls for reduced peak-to-peak voltage levels, as the sample rate increases and pushes up the output line rate.

The number of pins required for the same given converter resolution and sample rate is also considerably lower; see Table 1. There’s a synchronisation clock for each channel’s data for CMOS and LVDS outputs, and a maximum data rate of 4.0Gbps for JESD204B data transfer using CML outputs. The reasons for the progression to JESD204B using CML drivers become obvious when looking at Table 1, and observing the dramatic reduction in pin count that can be achieved.

Number of ChannelsResolutionCMOS
Pin Count
LVDS Pin Count
(DDR)
CML Pin Count (JESD204B)
11213142
21226284
41252568
81210411216
11415162
21430324
41460648
81412012816
11617182
21634364
41668728
81613614416
     

Table 1: Pin count comparisons for a 200MSPS ADC

Analog Devices has seen this trend to the JESD204 interface defined by JEDEC, being involved from the start. Analog Devices already offers several converters with JESD204- and JESD204A-compatible outputs and is currently developing products with outputs that are compatible with JESD204B.

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