• • 3 GSPS Speed: Operates thousands of times faster than standard monitoring tools. 
  • Instant Fault Detection: Captures transient power spikes in real time using on-chip digital signal processing. 
  • Zero On-Site Hassle: Delivers fully remote, event-based telemetry—eliminating the need for physical equipment in the server room. 
  • High-Voltage Power Help: Alongside the ADC, TI launched the LMI800PS (an 800V isolated hot-swap controller) to shrink complex multi-chip power designs down to a single package. 

In effect, the ADC34DSO75 is a module, consisting of two 14-bit ADCs based on a low-power pipelined architecture with IL x 2 to achieve 3GSPS.  Noise spectral density is -160dBFs/Hz and the device has internal calibration for interleaving correction, ENOB is > 10.5 bits.

Each ADC channel has a dedicated event detection engine to control data capture and storage to on the chip memory for offload via OSPI. There are a number of event detection modes including absolute high threshold, low threshold, high and low threshold derived from an aquired baseline, slope based triggering, and pin based triggering. Each ADC34DSO75 chip has a 256KiB memory which can be partitioned across the four channels of the ADC. Once an event is detected, the samples corresponding to the event can be written to the memory.

Along with the event data, an event header (96 bytes per event) is stored in the memory and contains information about the event captured such as the event mode, voltage at event, and timestamp. The number of samples to be stored for the events is programmable for each channel and is based on pre and post event window sizes. The events are timestamp via a 64-bit counter in the event detection engine running at the full sample clock rate. The device has per channel pins for pin based triggering of events and also event detection status on the pins. The ADC34DSO75 has two SYSREF outputs to enable simple mutli-device synchronization schemes.