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OpenHW Ecosystem implements Imperas RISC-V reference models for coverage-driven verification of CORE-V cores

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OpenHW Group establishes the CORE-V processor verification test-bench using the Imperas RISC-V reference model to deliver quality IP cores to the open-source hardware community.

Imperas Software develops virtual platforms and high-performance software simulation packages, whereas the OpenHW Group is a not-for-profit global organisation set up to facilitate collaboration between hardware and software designers in the development of open-source IP.

“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said Rick O’Connor, Founder and CEO at OpenHW Group. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”

Processor verification has four key parts: DV plan, tests to run, device-under-test (DUT) to test, and a reference model for comparison with discrepancy debug and resolution. Within the DV plan a number of metrics are used to record and monitor the overall progress, and in order to ensure a smooth conclusion, one of the key steps is the routine analysis and resolution steps as faults are identified and resolved. Only with a full and complete accounting as all the steps are completed can a DV team collaborate and complete the tasks within a timely and efficient timescale.

A common processor DV technique to test the complex states and extreme corner cases is to employ a random instruction stream generator, such as the popular Google open source project, RISCV-DV ISG as a test source and can be found on GitHub at https://github.com/google/riscv-dv. By setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, a step-and-compare methodology can be enabled. This avoids the inefficiencies of logfile based methods and supports direct analysis of any issues found. As a processor has a complex state-space, a step-and-compare approach also supports advanced techniques with dynamic testbenches using UVM (Universal Verification Methodology) and SystemVerilog stimulus/response features.

“The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution,” said Jingliang (Leo) Wang, Principal Engineer/Lead CPU Design Verification at Futurewei Technologies, Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.”

The OpenHW Group CORE-V Design Verification (DV) test plan is available at https://core-v-docs-verif-strat.readthedocs.io/en/latest/ together with the UVM testbench GitHub repository at https://github.com/openhwgroup/core-v-verif.

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