Search for the Next (SFN) now offers a family of four ITMs (Infrastructure Time Machine) that enable chip designers to produce ICs in older 180nm and even one-micron geometry fabs with the equivalent performance of CMOS devices made in current state-of-the-art plants. The compound combination of the Bizen wafer process, Zpolar transistor and Zpolar Tunnel Logic (ZTL), will, for example, enable a fab equipped with 180nm photolithographic steppers to produce ZTL devices with the performance (size, speed and performance) of 35nm CMOS by implementing ITM35 at highly reduced costs.
“Until Bizen, the Zpolar transistor and ZTL logic, high-performance chips for applications such as 5G and RISC-V could only be produced at facilities such as the Taiwanese giant, TSMC, which controls most of the world’s high-performance semiconductor production. Now, UK and other Western fabs can be competitive again, and even overtake the Taiwanese and Korean giants, while also securing best national interests and IP,” said Explains David Summerland, CEO of SFN.
SFN’s four ITMs include ITM180, which delivers ZTL chips with the performance of 180nm CMOS using one micron equipment; ITM35, which enables 35nm CMOS-equivalent ICs to be made in 180nm process node fabs; ITM5, which enables 5nm CMOS performance from 28nm steppers; and ITMSubnm, which leads to sub-nm, Angstrom-level capabilities for 3nm fabs . VHDL is taken into the chosen ITM, which delivers both the POR (Process Of Reference) and the GDSii for the resultant IC to the fabs. The Infographic shows this process.
Bizen applies quantum mechanics to any wafer process technology. Bizen ZTL chips require far fewer processing layers, enabling complex devices to be manufactured in large-geometry fabs around the world. Details Summerland: “A 180nm fab using ITM35 delivering ZTL chips with the equivalent performance of 35nm CMOS will have ten times fewer process steps than an actual 35nm CMOS process, resulting in a 10 fold reduction in production time. This translates into a 40-50 fold increase in net profit for the Bizen-converted fab. At the same time, this massively contributes to solving semiconductor shortages.”
Although a new technology, the Bizen process can run on standard silicon process technologies using standard CMOS processing equipment. Bizen has been in development at a UK fab for four years, and SFN has produced ‘gold standard’ test wafers, which have been characterized. The extracted characterization data has been put into a JMP data book and used to produce SPICE models which run in the Cadence design environment, and matches the results from the Synopsis wafer process flow.
“We are aware of CMOS technology roads stretching out to at least 2036 with device geometries down to two angstroms. It is important to understand CMOS is logic, MOS a transistor. Even CFETS are stacked nMOS and pMOS. Bizen/ZTL is a huge step forward and will render other complex approaches redundant. Zpolar transistors move away from a reliance on the unipolar structure of CMOS, to take advantage of an inherent hair trigger input and minimized vertical size. We believe ‘Time Machine’ is the best description for the compound combination of the Bizen wafer process, Zpolar transistor and Zpolar Tunnel Logic (ZTL): using this technology, IC designers can go back 10 years in manufacturing capabilities, then forward 10 years – or more – in performance terms, with the ZTL devices they create. Since the ICs are so much simpler to produce, and/or more chips can be made per wafer, we are also solving the semiconductor shortage crisis, and at the same time, eliminating our reliance on foreign powers and their roads. Where we’re going, we don’t need roads,” said Summerland.
