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Cascade multi-level inverter design

Feature

By Umut Özkaya and Levent Seyfi, Konya Technical University, Turkey

Inverter design is one of the outstanding issues in the field of power electronics. One of the most important studies in inverter design has been the multi-level topology. Multi-level inverters are used in many designs because of their working ability in high power and high efficiency alternative energy sources. Their advantages include low harmonics in the output voltage, low switching frequencies and high efficiencies, compared to conventional inverter designs.

Indispensable

Inverters have become an indispensable element in many industrial applications today, widely used in the control of various engine types and power systems, but also in battery-powered systems, fuel and solar cells, wind-turbines/micro-turbines, and more.

Their widespread use and the aim to make them even more efficient has led researchers to study them at a large scale, one of which is to obtain better quality output voltage and load current by keeping the number of switches at a minimum. Research has led to many new inverter structures and switching techniques.

In multi-level inverters, as the number of levels increases, the change in output voltage becomes similar to that of a sine signal, which helps achieve high-quality current and voltage.

Alternating current (AC) power supplies demand high power and low harmonics, when feeding a load or a network; it is desirable that the inverter output voltage waveform is sinusoidal since the harmonic levels are then low, achieved with multi-level inverter topologies.

Multi-level inverter topologies can be mainly classified into three groups: diode-clamped, flying-capacitor and cascaded, although there are others, such as cascaded transformers and cascaded half H-bridge inverters.

Since multi-level inverters have gradual voltage levels, the dv/dt voltage stress on the switching elements is low and the output voltage high. Low efficiency and electromagnetic interference problems arise due to the high switching frequency of the pulse width ratio (PWR) inverter and the imposing stress of the high dv/dt. As a result, an output filter must be used to reduce high switching frequency components and to obtain sinusoidal output voltage in series. Here, multi-level inverters compete with classic PWR inverters.

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