By Tim Ramsdale, CEO, Agile Analog
The semiconductor industry’s phrase “new design project” carries a rich set of connotations. It is commonly used to describe a development activity from scratch, rather than a re-design, cost-reduction tweak or any other modification of an existing design.
The reality, however, is that no new chip design ever starts with a completely blank canvas. Every ASIC or system-on-chip (SoC) design is a process of assembling and connecting building blocks and circuit elements that already exist in the form of IP developed and re-used in-house or from a third party, before any notionally ‘new’ design project begins. Still, there will be a small portion of the circuit that will be occupied by new circuit elements, which typically is the part that will take up most of the engineers’ time and effort to differentiate the design.
When it comes to IP in the analogue domain, experience shows that re-using existing IP is rarely as effective and trouble-free as first thought, partly because of its inherent difficulty of re-use and partly because there are some deficiencies in the way that IP has been supplied.
Re-using internal IP or procuring external IP is meant to help SoC or ASIC development teams get faster to a successful tape-out through optimised design. Existing IP should ideally reduce development effort and eliminate failures, saving time and costs.
When chip development begins, in evaluating third-party sources of analogue IP, specifying parts must be clear: say, a “12-bit ADC” for instance. But within this generic category, there must be a set of specifications that govern its IP’s implementation in the design – for an ADC this will be parameters such as operating voltage, sampling rate, linearity, noise, conversion speed, and more. Also, this IP must fit the fabrication and process node the development team has chosen. Hence, this set of specifications must be always unique, yet traditional third-party suppliers of analogue IP have not been providing it.
Analogue vs digital
The unfortunate mismatch between what customers want (analogue IP that is uniquely configured to match an application) and what the third-party analogue IP market supplies (standard, off-the-shelf product) has arisen because the analogue IP market has borrowed its business model from the digital IP world, and what works for digital IP is not well suited to analogue IP.
In digital electronics, functions can be specified in a clear-cut way: interfaces are standardised and configurability is available at RTL level, accessible to the user. This means that digital IP suppliers can create standard IP products that perform standard functions, but with some configurability for the chip integrator guaranteeing that IP with same functionality. One user’s instance of 256-bit AES hash cryptography, for example, will be substantially the same as every other user’s instance. Moreover, digital IP can be synthesised to the target process by the chip integrator. This means that digital IP suppliers can create a single instance of an IP product that is not only portable to many processes and nodes, but can be also easily optimised for speed, performance and power through the synthesis tools. Hence, digital IP suppliers can make a successful business out of creating a standard IP product which they sell many times to many customers.
This model does not work for analogue circuits because the fundamental characteristics of analogue systems are different. In a sensor, for instance, the requirements in relation to crucial parameters such as sensitivity, accuracy, precision, linearity or stability over temperature differ from application to application. In addition, optimising a single one of these results in trade-offs to the other – meaning that the super-set solution tends to consume more power and area than the application can allow.
What’s more, the behaviour of analogue circuits varies substantially from one fabrication process and node to another, even when made in the same foundry. So, whereas in the digital domain the cost of re-targeting is small thanks to digital synthesis, in the analogue world this cost is much higher – often approaching the cost to create original design. This then means that the conventional analogue IP supplier must choose to either provide standard, one-size-fits-all IP product or become a design services supplier. They are all unpalatable choices because, in the first instance, the customer fails to get IP that fits his specification, ending up with a sub-optimal design, and, in the latter instance, they must rework the IP for each design. Then, the economies of the IP market do not support a proper design services model: full-custom IP design is very expensive and can take up to two years to complete. Customers expect standard IP to be much cheaper than custom design, so the IP supplier takes shortcuts to minimise the time and effort in the rework of a ‘standard’ IP product. The result is the IP user receiving analogue IP that is not well verified, performs poorly and takes up precious internal development resources to optimise, which defeats the objective of buying in IP. Often, reworked versions of standard IP products are poorly supported by test data, qualification or documentation. All these issues have depressed the demand for analogue IP.
Fig. 1: The Agile Analog platform technology for generating IP unique to each customer and application
Interestingly, the same problems are encountered in internally-developed analogue IP projects. What’s needed are robust, high-performance design automation tools to assemble new IP from basic analogue circuit building blocks. Agile Analog has invented a new approach to analogue design automation, backed by the use of artificial intelligence, helping generate new, custom-designed analogue IP blocks with a fraction of the effort compared with conventional, manual, analogue circuit design.
The newly-generated analogue IP is still customised, however: it exactly matches the unique specifications set by the customer for the application and optimisation processes – speed, power consumption, die area and other parameters. The IP is compiled according to the specifications of the foundry’s Process Development Kit (PDK) for the foundry process and node selected by the customer. The process is entirely automated and typically takes fewer than 12 weeks from specification to provision of foundry-ready IP that is verifiable. The customer can evaluate and test the IP’s quality through the extensive deliverables provided during the generation process; see Figure 1. At every stage in the process, from functional description to verification to integration and testing, the customer receives detailed datasheets, simulations and test reports that fully document the performance and characteristics of the IP.
This breakthrough has remodelled the analogue IP supply chain; see Figure 2. Now, custom-configured IP can be generated in the time that it has previously taken to procure standard, off-the-shelf IP. The Agile Analog platform is qualified to generate IP in various functional domains, including linear power regulation, temperature sensing, reference generation, tamper detection and data conversion. The development roadmap will see continual expansion of the domains supported by the platform.
Fig. 2: A new set of capabilities underpins Agile Analog’s remodelling of the analogue IP supply chain
The generated IP is compatible with almost any CMOS process, and is currently running on a broad set of nodes including FinFET processes down to 12nm. If the node, process or foundry change mid-design, the platform easily accommodates that by re-optimising and recompiling for the new process in a matter of days.
Relying on commercial analogue IP
With standard analogue IP products, customer engagement involves finding the standard product variant that is the closest match to the application’s requirements. In other words, it is a question of finding the least bad compromise.
Agile Analog’s technology has enabled a new approach to the procurement of analogue IP, one in which the specification process becomes more interactive. This means that, for the first time, commercial analogue IP can perform the functions it is supposed to do, easily integrated into and optimised for chip designs and fabrication processes, in effect freeing the design team to focus on the unique, added-value functionality for which there is no third-party IP.