By Paolo Novellini, Principal Engineer, Xilinx
Many applications would simply not exist without synchronisation – the timing coordination of events to operate systems in unison. Synchronisation is the technology that keeps local clock copies (slaves) aligned to a common reference (master) over time. Without synchronisation, systems will fail to operate properly.
While the term synchronisation identifies the general technology, the criteria are strictly related to the applications. In Xilinx’s Versal Adaptive Compute Acceleration Platform (ACAP) there are two specific metrics relating to synchronisation: 1. accuracy and precision, and 2. integration.
Although many interchange the terms accuracy and precision, in measurement theory they have different meanings, independent from each other. A measurement system is “precise” if repetitive measurements of the same target give results close to each other, even if not correct. Whereas it is “accurate” if repetitive measurements of the same target give results that are on average correct.
Consider Figure 1, where we want to measure its position of an object (the red dot). Two instruments (blue and green) are used for the measurement, with the cluster of blue dots representing the blue instrument’s measurements and the green dots that of the green instrument.
Figure 1: Precision and accuracy
Based on these definitions, the green instrument is more accurate than the blue one, whilst the blue is more precise than the green. It also means that averaging is a good way to assess the position of an object only if the measurement system is accurate – if not, calibration is the only suitable solution.
The parameters that most lead to inaccuracies in the local clock copy come from the electronics, and specifically from the transceiver FIFOs. This is because the transceiver’s FIFO has a latency that changes at each start-up, and one that depends on its PVT (process, voltage, temperature). These two must be considered separately since they influence accuracy differently. The first one impacts accuracy directly: if a receiver and a transmitter have different latency at start-up, the IEEE1588 mechanism will not detect it and any unbalancing will directly impact accuracy – even averaging will not help. Notice in Figure 3 that both measurement sets are biased.
The second effect, surprisingly, has no impact on accuracy. In fact, the latency variations due environment conditions (voltage, temperature, etc.) will apply to both receiver and transmitter and the IEEE1588 mechanism will cancel them out. This, however, does not mean that the time transfer should occur only once after start-up. If we calibrate only once, the change in latency, although symmetrical between RX and TX, will produce an error in the slave clock, which will then build up with the temperature/supply drift. The countermeasure is to re-sync at a pace faster than the temperature/supply change.
Xilinx’s Versal transceivers offer alternative methods to measure and control latency, both at start-up and during runtime, which fall into two categories: buffer bypass and FIFO latency measurement. The first allows bypassing the FIFO in both RX and TX direction, setting up a sophisticated clocking scheme to handle the data domain crossing with no timing errors. It also has minimal latency, which, although many not be relevant for synchronisation applications, is key for other industry fields, such as high-frequency trading (HFT), for example.
Figure 2: Start up to start-up latency variation
While buffer bypass solves the problem by setting the transceiver latency to a fixed value, another very interesting set of techniques focuses on measuring the latency itself. If the latency is known at any given point in time, it can be easily reused to mathematically correct the value of ‘the time of the day’ or TOD. This method is very interesting in synchronisation applications, since it offers a natural upgrade path for all IPs (for example, Ethernet) with no relevant change in the clocking architecture of the IP itself.
Precision is achieved in both approaches because the platform uses a hardcoded analogue phase detector built in the transceiver and analogue phase interpolators, controlled by the user, who can step up or down the clock phases with picoseconds-long increments.
The typical source of inaccuracy is the startup-to-startup change in latency due to the random phase that dividers can have after reset. Versal allows to either measure or set the latency at start-up. This initial calibration stage ensures all sources of inaccuracy in the transceiver are removed.
The variation of latency (symmetrical for RX and TX) that occurs during runtime can be compensated by the precision time protocol (PTP) mechanism itself, which begs the question, what is the advantage of measuring latency over time?
There are many cases where the change in latency is not symmetrical between RX and TX, for example in passive optical networks (PONs) used in telecoms. In other cases, the RX and TX paths can be on different physical devices, for example in test equipment. Different devices might happen to be at different temperature, process and power supply, which would yield a different trend in latency over time between RX and TX, giving rise to inaccuracy.
The Versal ACAP is a game changer in transceiver latency control and latency measurement: from the nanosecond level of typical fabric clocks to the picosecond level offered by hardcoded analogue phase interpolators.
And, lastly, when referring to “synchronisation application”, it’s worth noting that this is any application that leverages the ability to transfer the TOD between network nodes falls into this category and is very user-specific. In the general case it requires processors with proprietary software, a compute logic and different interfaces. In many cases it requires even fast ADC or DACs and/or DSP engines.
With Versal, system architects and designers will be able to implement their own application, with their own expertise, in a single device. It is the easiest and fastest way to bring your ideas to life – the full application can run on one chip, accurately synchronised.