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Verification challenges in the JESD204B standard for high-speed data converters – Part 1


By Frank Farrelly, Product Engineering Manager, Analog Devices, and Chris Loberg, Senior Technical Marketing Manager, Tektronix

The world of data converters is evolving: As the bit depth and sample rate go up, getting data in and out becomes increasingly difficult. A decade or two ago, with sample rates for high-speed converters limited to 100MSPS, using TTL or CMOS parallel data buses was sufficient. For example, a 12-bit converter with 12 pins dedicated to data could be implemented with reasonable setup and hold times with respect to the clock.

As speeds increased above 100MSPS, setup and hold times for single-ended signals could no longer be maintained. To boost speeds, high-speed converters moved to differential signalling but at the cost of increased pin counts. For example, a 12-bit converter would now need 24 pins dedicated to data.

To address the pin count issue, serial data interfaces were adopted. A converter data interface with 6× serialisation now allows that same 12-bit converter to transfer the data with just two differential I/Os (only four pins). Fast forward to today, and converters are being developed using the JESD204B specification for the data interface. The JEDEC standards organisation has published two versions of the JESD204 high-speed serial digital interface specification: The first (JESD204 2006), brought the advantages of SerDes-based high-speed serial interfaces to data converters with a 3.125Gbps maximum speed rating. Its revision in 2008 (JESD204A 2008) added important enhancements, including support for multiple data lanes and lane synchronisation. The second version of the specification, JESD204B, was developed by an international JEDEC JC-16 task group (Project 150.01), to provide enhancements such as a higher maximum lane rate, support for deterministic latency through the interface, and support for harmonic frame clocking.

Lack of compliance test specification

Unlike many other high-speed serial interface standards, JESD204B does not include an official compliance test specification. A test specification is doubly valuable because it lists the tests that must be performed to ensure compatibility, as well as the procedures for performing them. Having consistent procedures used by different manufacturers ensures a common understanding of the specification and eliminates differences in assumptions.

However, not all is lost: the information needed to develop a set of tests and procedures can be found in the JESD204B specification. It is left up to the individual chip manufacturers and system developers to pull together that information.

Physical layer testing

Physical layer, or PHY, tests relate to the individual data lane driver and receiver circuitry: i.e., the analogue tests of a link. They do not include digital functionality or procedural tests.

Working toward the goal of developing a thorough list of PHY tests, or a list of recommendations, SerDes PHY tests can be obtained from the OIF-CEI-02.0 specification, section 1.7. The JESD204B specification closely follows those recommendations, but with some modifications. For example, JESD204B does not specify random jitter as a standalone test item, but includes it under total jitter. Also, JESD204B specifies JSPAT, JTSPAT and modified RPAT as recommended test patterns, whereas the OIF-CEI-02.0 specifies using the PRBS31 pattern.

There are additional PHY tests that could be performed that are not listed in the OIF-CEI-02.0 or JESD204B specifications. Other SerDes compliance test specifications include other PHY tests such as intrapair skew (for a transmitter) and intrapair skew tolerance (for a receiver). However, additional PHY tests are not required to ensure JESD204B compatibility; the intention is to use other tests to gain insight as to why a particular PHY test has failed.

Once the list of tests is set, limits for those tests can be obtained from the JESD204B specification and there are three sets of them: LV-OIF-11G-SR, LV-OIF-6G-SR and LV-OIF-SxI5. A particular JESD204B device may support more than one set of limits, in which case the component should be tested against all supported limit sets.

One point of potential confusion with JESD204B PHY testing is jitter terminology, since JESD204B and OIF-CEI-02.0 use different terminology to that of the test equipment vendors. The typical jitter map is shown in Figure 1. Test equipment makers base their terminology on the industry standard dual-Dirac jitter model. This difference in terminology is a point of potential problems in test procedures, as jitter is quite a tricky topic. Table 1 shows our translation of the jitter terminology (the JESD204B specification uses different terminology for jitter from that used by test equipment vendors).

JESD204B Jitter TermJESD204B Jitter NameTest Equipment Jitter and Translation
T_UBHPJTransmit uncorrelated bounded high probability jitterBUJ (PJ and NPJ)
T_DCDTransmit duty cycle distortionDCD
T_TJTransmit total jitterTJ
R_SJ-HFReceive sinusoidal jitter, high frequencyPJ > 1/1667 × BR
R_SJ-MAXReceive sinusoidal jitter, maximumPJ < 1/166,700 × BR
 Receive bounded high probability jitter—correlatedDDJ
R_BHPJReceive bounded high probability jitter—uncorrelatedNPJ
R_TJReceive total jitterTJ

Table 1: Jitter terms translation

Another point of potential confusion with JESD204B PHY testing is the eye mask for data rates above 11.1Gbps. The JESD204B specification says that for data rates above 11.1Gbps to use a normalised bit time of 11.1Gbps. So, if running at 12.5Gbps (with an 80ps bit period), it says to use the bit period for 11.1Gbps (90.9ps). The issue is that eye masks can be built by starting either at the edge of the UI or from the UI centre, and the JESD204B does not clearly state which reference to use. If at the UI centre, then at 12.5Gbps the eye mask is bigger than normal, making it harder for a transmitter to pass but easier for a receiver to work. If the reference point is the edge of the UI, then at 12.5 Gbps the eye mask is smaller than normal, making it easier for a transmitter to pass but hard for a receiver to work. Ultimately, until this question is resolved, it is recommended to test against each of the two mask options to ensure compatibility.

Timing testing

Coming up with a thorough list of timing tests for JESD204B is not an easy task. There are at least dozen timing diagrams in the specification, and it’s not immediately apparent which ones apply to the transmitter, channel or receiver. Also, some are only applicable to a particular subclass (0, 1 or 2).

An official compliance test specification would be especially helpful here if it were to simply consolidate the timing specifications into a single table, removing confusion.

One benefit for developers is that specifying timing for a JESD204B component is easier than specification implies. For Subclass 0 and 2, only device clock-to-SYNC~ timing must be specified; for Subclass 1, it’s only device clock-to-SYSREF timing.

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