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JESD204B: What can go wrong?

Series

By Anthony Desimone, Applications Engineer, and Michael Giancioppo, Applications Engineer, Analog Devices

JESD204B can be a complicated interface standard, with many operational subtleties. Finding out why it is not working requires a good understanding of likely scenarios. It is not an inclusive guide but provides a good basic baseline for an engineer working with and wanting to learn about a JESD204B link.

1.     Stuck in CGS mode: if SYNC stays at logic low level; or pulse high for <4 multiframes

 

Checking the board, unpowered:

  • SYSREF and SYNC~ signalling should be DC coupled.
  • With the board unpowered, check that the board SYNC~ connections from the SYNC~ source (typically from the FPGA or DAC) to the SYNC~ input (typically ADC or FPGA) are good and low impedance.
  • Check that the pull-down or pull-up resistors are not dominating the signalling, for example, if values are too small or shorted and, therefore, cannot be driven correctly.
  • Verify that the differential-pairs traces (and cables, if used) of JESD204B link are matched.
  • Verify differential impedance of the traces is 100 Ω.

Checking the board, powered:

  • If there is a buffer/translator in the SYNC path, make sure it is functioning properly.
  • Check that SYNC~ source and board circuitry (both SYNC+ and SYNC−, if differential) are properly configured to produce logic levels compliant for the SYNC~ receive device. If logic level is not compliant, then review circuitry for source and receive configurations to find the problem. Otherwise, consult device manufacturer.
  • Check that the JESD204B serial transmitter and board circuitry are properly configured to produce the correct logic levels for the JESD204B serial data receiver. If logic level is not compliant, review circuitry of source and receive configurations to find the problem. Otherwise, consult device manufacturer.

Checking SYNC~ signalling:

  • If SYNC~ is static and logic low, the link is not progressing beyond the CGS phase. There is either an issue with the data being sent, or the JESD204B receiver is not decoding the samples properly. Verify /K/ characters are being sent, verify receive configuration settings, verify SYNC~ source, review board circuitry, and consider overdriving SYNC~ signal and attempt to force link into ILAS mode to isolate link receiver vs. transceiver issues. Otherwise, consult device manufacturer.
  • If SYNC~ is static and logic high, verify the SYNC~ logic level is configured correctly in the source device. Check pull-up and pull-down resistors.
  • If SYNC~ pulses high and returns to logic-low state for less than six multiframe periods, the JESD204B link is progressing beyond the CGS phase but not beyond ILAS phase. This would suggest the /K/ characters are fine and the basic function of the CDR are working. Proceed to the ILAS troubleshooting section.
  • If SYNC~ pulses high for a duration of more than six multiframe periods, the link is progressing beyond the ILAS phase and is malfunctioning in the data phase; see the data phase section for troubleshooting tips.

Checking serial data

  • Verify the transceiver’s data rate and the receiver’s expected rate are the same.
  • Measure lanes with high impedance probe (differential probe, if possible); if characters appear incorrect, make sure lane differential traces are matched, the return path on the PCB is not interrupted, and devices are properly soldered on the PCA. Unlike the (seemingly) random characters of ILAS and data phase, CGS characters are easily recognisable on a scope (if a high enough speed scope is available).
  • Verify /K/ characters with high impedance probe.
  • If /K/ characters are correct, the transceiver side of the link is working properly.
  • If /K/ characters are not correct, the transceiver device or the board Lanes signal have an issue.
  • If DC coupled, verify that the transmitter and receiver common-mode voltage is within specification for the devices
  • Depending upon implementation, the transmitter common-mode voltage can range from 490-1135mV.
  • Depending upon implementation, the receiver common-mode voltage can range from 490-1300mV.
  • Verify the transmitter CML differential voltage on the data lanes (note that the CML differential voltage is calculated as two times the voltage swing of each leg of the signal).
  • The transmitter CML differential voltage can range from 0.5-1.0Vp-p for speeds up to 3.125Gbps.
  • The transmitter CML differential voltage can range from 0.4-0.75Vp-p for speeds up to 6.374Gbps.
  • The transmitter CML differential voltage can range from 0.360-0.770Vp-p for speeds up to 12.5Gbps.
  • Verify the receiver CML differential voltage on the data lanes (note that the CML differential voltage is calculated as two times the voltage swing of each leg of the signal).
  • The receiver CML differential voltage can range from 0.175-1.0Vp-p for speeds up to 3.125Gbps.
  • The receiver CML differential voltage can range from 0.125-0.75Vp-p for speeds up to 6.374Gbps.
    • The receiver CML differential voltage can range from 0.110-1.05Vp-p for speeds up to 12.5Gbps.
  • If pre-emphasis is an option, enable and observe data signals along the data path.
  • Verify that the M and L values match between the transmitter and receiver, otherwise the data rates may not match. For example, M = 2 and L = 2 will expect half the data rate over the serial interface as compared to the M = 2 and L = 1 case.
  • Ensure the device clock going to the transmitter and receiver is phase locked and at the correct frequency.

2.     Can’t get beyond ILAS mode if SYNC pulses high for approximately four multiframes

  • Link parameter conflicts.
    • Verify link parameters are not offset by 1 (many parameters are specified as value −1).
    • Verify ILAS multiframes are transmitting properly, verify link parameters on the transceiver device, the receiver device and those transmitted in ILAS second multiframe.
    • Calculate expected ILAS length (tframe, tmultiframe, 4 × tmultiframe), verify ILAS is attempted for approximately four multiframes.
  • Verify all lanes are functioning properly. Ensure there are no multilane/multilink conflicts.

3.     Get into data phase but occasionally link resets (returns to CGS and ILAS before returning to data phase)

  • Invalid setup and hold time of periodic or gapped periodic SYSREF or SYNC~ signal.
  • Link parameter conflicts.
  • Character replacement conflicts.
  • Scrambling problem, if enabled.
  • Lane data corruption, noise, or jitter could force the eye diagram to close.
  • Spurious clocking or excessive jitter on device clock.

 

4.     Other general tips when troubleshooting link:

  • Run converter and link at the slowest allowed speed, as this allows use of lower bandwidth measurement instruments that are more readily available.
  • Set minimum allowed combinations of M, L, K, S.
  • Use test modes when possible.
  • Use Subclass 0 for troubleshooting.
  • Disable scrambling while troubleshooting.

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