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FD-SOI process and optimised architecture combo helps Lattice Semiconductor lower the power and improve the performance of its FPGAs


Aiming to address the needs of safety-critical applications, embedded vision and smart everything, FPGA vendor Lattice Semiconductor has turned to a semiconductor process technology called fully-depleted silicon-on-insulator (FD-SOI) on a 28nm node to bring power consumption down and performance up of its programmable logic.

“Our new Nexus platform based on the 28nm FD-SOI technology from Samsung, combined with our low-power FPGA architecture, offers 75% less power consumption than other comparable solutions,” said Gordon Hands, Marketing Director at Lattice Semiconductor.

FD-SOI technology offers many advantages over standard bulk silicon. Unlike in bulk silicon, an FD-SOI transistor has a very thin silicon layer, or its channel, on top of a buried oxide (see image). This layer is not doped to carry current, hence “fully depleted”. Not having any charges reduces the risk of leakage current that may switch on the transistor when not needed, but also lowers the risk of soft errors, where a naturally occurring energy particles might switch the transistor on or off at the wrong time or flip a bit in the memory. The buried oxide layer further isolates the transistor’s source from its drain, lowering the parasitic capacitance between them. Overall power consumption is reduced in an FD-SOI device.

Likewise, compared to bulk silicon, FD-SOI performs better at reduced silicon geometries, and offers more efficient biasing, allowing designers to dynamically raise or lower the threshold voltage and further optimise the power and performance of the transistor.

Based on its newly-launched Nexus platform, Lattice also announced its new FPGA, named CrossLink-NX. Among its significant features are its ‘instant on’ performance, where I/O configuration takes only 3ms from power-up, with a further 12ms for a complete device configuration; expanded memory of 170 bits per logic cell; a soft error rate (SER) up to 100 times lower than that of other FPGAs; on-point I/O offering (MIPI, PCIe and DDR3 memory), and full support with software tools.

Lattice’s Hands says that the Nexus platform offers great improvements in power and performance due to the FD-SOI’s nature, the Lattice-optimised FPGA architecture, which by not having external memory further helps with device speed and reduced power consumption, and because the designers themselves can further tweak the device’s parameters.

Lattice has been super-fast in delivering its CrossLink-NX product, which is sampling now yet was originally planned for 2020.

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