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eMemory’s NeoFuse one-time programmable memory suitable for Advanced AI and HPC devices

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eMemory’s one-time programmable (OTP) memory, NeoFuse, has been qualified on the TSMC N3P process – a 3nm process node for improved power and performance and greater density.

NeoFuse OTP on TSMC’s N3P process delivers secure performance with support for up to 4K x 40 bits density and a wide operating voltage range of 0.55V to 0.96V. These capabilities enable high-capacity data storage and reliable system design, essential for AI SoCs, HPC processors, automotive electronics, and other applications requiring high-density embedded memory.

“The qualification of NeoFuse OTP on TSMC’s N3P process highlights the achievement of our collaboration in supporting mutual customers and reflects our long-term commitment to high-performance and security-critical applications,” said Chris Lu, Senior Vice President of Business Development of eMemory. “We will continue to drive ongoing innovation in NVM technologies on advanced process nodes.”

Built upon this foundation, a security-enhanced version of NeoFuse OTP, integrated with NeoPUF, eMemory’s patented physical unclonable function (PUF) technology, not only significantly strengthens security and design flexibility but also helps customers reduce development efforts and accelerate time-to-market. Centred around a comprehensive, system-level OTP solution, this version seamlessly integrates with fully verified controllers and supports error correction code (ECC) and voting mechanisms to enhance memory system reliability and ensure data integrity. Combined with a fully verified wrapper design and integrated APIs, including a standard APB interface and a dedicated MBIST interface for SRAM repair, it enables true random number generation (TRNG) for hardware-level protection while strengthening system integration, memory self-testing, and rapid data recovery capabilities. These features support critical functions such as secure boot, root of trust, device authentication, and key management, greatly enhancing chip-level attack resistance, improving yield, and speeding up product launch.

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