By George Diniz, Product Line Manager, Analog Devices
The JESD204A/JESD204B industry standard for serial interfaces was developed to address the problem of interconnecting the latest wideband data converters with other system ICs in an efficient and cost-saving way. The motivation was to standardise an interface that would reduce the number of digital inputs/outputs between data converters and other devices, such as field programmable gate arrays (FGPAs) and system-on-a-chip (SoC) devices, through scaleable high-speed serial interface.
Trends show that new applications – as well as advances in existing ones – are driving the need for wideband data converters with increasingly higher sampling frequencies and data resolutions. Transmitting data to and from these wideband converters poses a significant design problem, since bandwidth limitations of existing I/O technologies require higher pin counts on converters. Consequently, system PCB designs have become increasingly complex in terms of interconnect density. The challenge is routing a large number of high-speed digital signals whilst managing electrical noise. The ability to offer wideband data converters with GSPS sampling frequencies with fewer interconnects, simplifies the PCB layout challenges and allows for compact systems without affecting performance.
Market forces continue to press for more features, functionality, performance and higher data-handling capacity in a given system. The high-speed analogue-to-digital converter (ADC) and digital-to-analogue converter (DAC) to FPGA interface had become a limiting factor in data-intensive applications. The JESD204B serial interface specification was specifically created to help solve this problem by addressing this critical data link. Figure 1 shows typical high-speed converter-to-FPGA interconnect configurations using JESD204A/JESD204B.
Figure 1: Typical high-speed converter to FGPA interconnect configurations using JESD204A/JESD204B interfacing
Need for JESD204B
There are some applications that drive the need for the JESD204B standard, including:
– Wireless infrastructure transceivers
OFDM-based technologies, such as LTE, used in today’s wireless infrastructure transceivers, use DSP blocks implemented on FPGAs or SoC devices driving antenna array elements to generate beams for each subscriber handset. Each array element may move hundreds of megabytes of data per second between FPGAs and data converters in both transmit or receive mode.
– Software-defined radios (SDR)
Today’s SDRs utilise advanced modulation schemes that can be reconfigured on the fly, with rapidly increasing channel bandwidths to deliver unprecedented wireless data rates. Efficient, low-power, low-pin-count FPGA-to-data converter interfaces in the antenna path play a critical role in their performance.
SDR architectures are integral to the transceiver infrastructure for multicarrier, multimode wireless networks supporting GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX and TD-SCDMA.
– Medical imaging systems
Medical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI) and others generate many channels of data that flow through a data converter to FPGAs or DSPs. An increasingly-growing number of I/O counts is driving the number of components by requiring interposers to match FPGA and converter pinouts, and, also, increase PCB complexity and costs. The JESD204B interface is much more efficient.
– Radar and secure communications
Increasingly-sophisticated pulse structures on today’s advanced radar receivers are pushing signal bandwidths toward 1GHz and beyond. Latest-generation active electronically-scaled array (AESA) radar systems may have thousands of elements. High-bandwidth SERDES-based serial interfaces are needed to connect the array element data converters to the FPGAs or DSPs that process incoming data streams and generate outgoing ones.
Serial LVDS or JESD204B?
To choose the best product for the application, a comparison of features and capabilities of LVDS and the various versions of the JESD204 serial interface is shown in Table 1.
At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing high-level features like multidevice synchronisation, deterministic latency and harmonic clocking, JESD204B is the only interface that provides these functionalities. Systems requiring wide-bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won’t be able to effectively use LVDS or parallel CMOS.
|Maximum Lane Rate (Gbps)||1.0||3.125||3.125||12.5|
Table 1. Comparison between serial LVDS and JESD204 specifications
LVDS is the traditional method of interfacing data converters with FPGAs or DSPs. It was introduced in 1994 to provide higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards.
LVDS was standardised with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard revised with the publication of TIA/EIA-644-A in 2001.
LVDS uses differential signals with low voltage swings for high-speed data transmission. The transmitter typically drives ±3.5mA with polarity matching the logic level to be sent through a 100Ω resistor, generating a ±350mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655Mbps, although it predicts a possible speed of over 1.9Gbps for an ideal transmission medium.
The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier, has created several issues with the LVDS interface; see Figure 2. The bandwidth of a differential LVDS wire is limited to about 1.0Gbps in the real world. In many current applications this creates the need for a substantial number of high-bandwidth PCB interconnects, each of which being a potential failure point. The large number of traces also increases PCB complexity and overall size, raising design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth-hungry applications.
Figure 2. Challenges in system design and interconnect using parallel CMOS or LVDS
The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology to provide a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high-speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communication at a much higher speed.
In 2006, JEDEC published the JESD204 specification for a single 3.125Gbps data lane. The JESD204 interface is self-synchronous, so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SERDES ports offered on many FPGAs to free up general-purpose I/O.
JESD204A, published in 2008, adds support for multiple time-aligned data lanes and lane synchronisation. This enhancement makes it possible to use higher bandwidth data converters and multiple synchronised data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multidevice synchronisation support that is useful for devices that use large numbers of ADCs, such as medical imaging systems.
JESD204B, the third revision of the spec, increases the maximum lane rate to 12.5Gbps. JESD204B also adds deterministic latency, which communicates synchronisation status between receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high-speed data converter clock from a lower-speed input clock with deterministic phasing.
Fewer interconnects simplify layout and make it possible to achieve a smaller form factor; see Figure 3.
Figure 3. JESD204 with its high-speed serial I/O capability solves the system PCB complexity challenge