CEA-Leti has just introduced a Fully Depleted Silicon On Insulator (FD-SOI) pilot line to advance chip making.
FD-SOI is a planar CMOS technology that offers the best PPAC-E (Performance, Power, Area, Cost and Environmental impact) for mixed circuits (mixing digital, analogue and radio-frequency blocks). It offers tight electrostatic control at the transistor level and is well suited for power management.
The booming FD-SOI market is therefore anticipating the 10nm and 7nm next-generation nodes.
“By integrating and combining a set of cutting-edge technologies, the FAMES pilot line will open the door to disruptive system-on-chip architectures and provide smarter, greener and more efficient solutions for future chips. The FAMES project will indeed pay special attention to semiconductor sustainability challenges,”
said Jean-René Lèquepeys, CTO of CEA-Leti.
The line is also supported by the European semiconductor ecosystem, called Chips JU.
“The Chips Joint Undertaking (Chips JU) is proud to contribute to this strategic initiative and strengthen the EU’s sovereignty in a critical domain. This pilot line will advance essential semiconductor technologies, while maintaining a strong focus on sustainability, and foster the collaboration between several European actors. The Chips JU aims to act as a catalyst and a model for further public and private collaborations in key areas,” explained Jari Kinaret, the Chips JU executive director.
The FAMES Consortium brings together companies including Imec (Belgium), Fraunhofer Mikroelektronik (Germany), Tyndall (Ireland), VTT (Finland), CEZAMAT WUT (Poland), UCLouvain (Belgium), Silicon Austria Labs (Austria), SiNANO Institute (France), Grenoble INP-UGA (France) and the University of Granada (Spain).
The five new technologies will create market opportunities for low-power microcontrollers (MCU), multi-processor units (MPU), cutting-edge AI and machine learning devices, smart data-fusion processors, RF devices, chips for 5G/6G, chips for automotive markets, smart sensors and imagers, trusted chips and new space components.
The pilot line will be accessible to all EU stakeholders (universities, RTOs, SMEs and industrial companies)
and all like-minded countries through annual open calls and upon request, following a fair and non-discriminatory selection process.
The project will benefit from funding that will be provided in equal parts by participating member states and the Chips JU.
