Siemens Digital Industries Software announced today a fully automated solution to help integrated circuit (IC) design teams rapidly identify and address Electrostatic Discharge (ESD) issues driven by the growing complexity of today’s next-generation IC designs, regardless of targeted process technology. Combining the power of Siemens’s Calibre PERC software with the proven SPICE accuracy of its AIpowered Solido Simulation Suite, it provides a fast and highly accurate method for checking compliance against foundry rules spanning all phases of IC design.
Supporting fullchip level verification, the solution helps engineering teams better manage design and manufacturing challenges in both established and emerging process nodes. Its contextaware checks can help to improve the accuracy of results, while reducing turnaround time for physical, circuit, electrical and reliability IC design verification.
The solution’s contextaware checking allows design teams to verify ESD paths quickly, in time to secure waivers from foundry rules that can lead to smaller die sizes and optimized designs, ultimately helping design teams quickly arrive at data driven decisions 8x faster than current methods.
Foundry ESD rules are designed to prevent ESD failures, while accommodating the diverse design styles submitted by fabless companies globally. However, these rules may be overly conservative for specific design styles and mission profiles. By rapidly identifying and simulating ESD paths that might fail foundry rules with detailed transistorlevel breakdown models, this Siemens’ new software identifies atrisk paths with SPICElevel precision, allowing for fast, targeted and automated fixes.
“Siemens’s new contextaware ESD simulation solution can help deliver accurate reliability assessment for complex IC designs,” said Silicon Labs’ Michael Khazhinsky, Principal ESD Engineer of Central R&D. “The pushbutton solution integrates dynamic simulation results from Solido into a fullchip Calibre PERC result that can be used to quickly determine if designs are electrically robust. In the event of circuit errors, this Siemens solution identifies nets and devices that need to be improved.”
Automated contextaware IC design verification can now become a best practice, helping the quick delivery of reliable and timely IC chips to market. Featuring functionalities such as automated voltage propagation, voltageaware design rule checking, and the integration of physical and electrical information within a logicdriven layout framework, it helps design teams working to tight schedules.
“By leveraging automated contextaware checking, Siemens is empowering design teams to address more quickly the complexities of modern IC design reliability verification,” said Michael BuehlerGarcia, vice president of Calibre Product Management at Siemens Digital Industries Software.” This integration combines the strengths of our dynamic simulation from Solido and signoff level ESD verification in Calibre PERC. Our integrated solution speeds up the verification process while at the same time ensuring the reliability of IC designs, helping our customers achieve their goals more efficiently. This is the first in a series of solutions that Siemens plans to provide that leverage offerings from different elements of our software portfolio to speed overall design cycle time.”
