A correct implementation of TSN must provide a low latency and deterministic response at TSN end points and switches. The accurate timing for the transmission of scheduled Ethernet frames requires dedicated circuitry such as the programmable logic found in FPGAs. Heterogeneous SoCs which combine high performance processors with this programmable logic are ideal for high performance embedded vision and IIoT solutions, and provide any-to-any interfacing capability thanks to the flexibility of programmable logic. This enables developers to leverage the increase in performance, response time and determinism which comes with the use of programmable logic, while leaving the high-performance processors to implement the higher-level communication and application functionality.
The combination of processor system and programmable logic also enables the implementation of TSN within a single device, helping to achieve the SWaP-C which is so critical for the Industry 4.0 embedded vision applications.
Example Solution
One example TSN implementation is to use a Zynq®-7000 or Zynq® UltraScale+™ MPSoC device utilising both the Processing System (PS) and the Programmable Logic (PL). Xilinx’s TSN Endpoint Ethernet MAC LogiCORE™ IP supports Ethernet with 100 Mbit/s (Fast Ethernet) and 1000 Mbit/s (Gigabit Ethernet). It comprises programmable logic for MAC, TSN Bridge and TSN Endpoint, along with software components for network synchronisation, for initialisation and for interfacing with network configuration controllers for stream reservation. The software is designed to run on PetaLinux and will be published as Yocto patches.
The LogiCORE IP, built with dedicated resources from the device’s PL, provides deterministic behaviour for synchronisation (IEEE 802.1AS), scheduled traffic (IEEE 802.1Qbv) and seamless redundancy (P802.1CB), while also helping with offloading from the processing unit.
The IP core also comes with an optional integrated time-aware L2 switch that creates the chain or tree topology that is required in many industrial applications, without allocating another port at an external TSN switch. Seamless redundancy (P802.1CB) is then feasible as it requires the additional port. The user can freely configure before synthesis if the switch shall be integrated or not.
The TSN IP core provides individual interfaces for each traffic class and these are used in conjunction with the processors, DDR memory and interconnect within the PS. These AXI Stream interfaces support scheduled, reserved and best effort / legacy traffic over the network.
The AXI infrastructure is ideal for high bandwidth communication to the processing system. Direct Memory Access for each of the traffic classes manage the data stream. AXI Lite is used to perform initialisation and configuration of the TSN subsystem.
Not all TSN sub-standards are fully adopted today but the reconfigurability of programmable logic provides the benefit of enabling updates to the TSN subsystem LogiCORE IP core as the TSN standards are finalised.
Wrapping it up
To enable deployment of embedded vision within Industry 4.0 applications, systems need to be able to connect with converged IIoT networks. TSN is one commonly used standard for this. Implementing TSN within an All Programmable Zynq-7000 or Zynq UltraScale+ MPSoC device creates a single chip solution, which can also provide the processing capability and interfacing ability in the PS and PL to perform the embedded vision application.
For more information, please visit: http://www.xilinx.com/products/design-tools/embedded-vision-zone.html
