By Susan Mack, Senior Engineering Manager at Sondrel Designing the front end of a chip is generally seen as more fun than, say, its verification. And, yet, chip verification is a crucial part of the design process and can take up as much as 70% of the time. Typically, after a design is created, verification engineers test it thoroughly, which is where exciting and interesting challenges lie. Real life can create unusual scenarios for a chip and a verification engineer’s job is to find ways to test each design to make sure it will perform correctly whatever the setup. And as chips become larger and more complex, it is vital to automate and re-use verification tools and methodologies for speed and comprehensiveness. This is particularly important as some chips can have mission-critical roles, such as in autonomous cars for example, hence they must perform correctly at all times. A million-to-one event could be disastrous if the chip does not behave correctly. An interesting new area in verification is blending C-based SoC integration verification with horizontal and vertical re-usability mechanisms. These are created on C-based verification flows and components on the IP level first, then sub-system level and, finally, the entire SoC, which avoids creating use cases specifically for each level. Not only are test scenarios created for vertical reusability, the verification plans that detail them check and develop the coverage points required for reuse. The plan clearly indicates these points, which are incorporated in the verification of a particular level. This allows to identify suitable tests quickly, which ensures correct component integration, saving time and reducing errors. With horizontal reusability, instead of running a simulation test at a particular level that could take many days, emulation takes only a few hours. Test benches help transition from simulation to emulation quickly and easily via the SCE-MI interface, massively saving time over many tests. Random behaviour Meeting functional safety standards for electronics, such as ISO26262 for automobiles, is a key part of verification. In ISO26262, there are two types of faults: systematic and random failures. The systematic failures are those historically looked for, relating to bugs found during development and manufacturing. Random failures can come from the degradation of parts as well as environmental effects, which can cause a design to mis-behave. Radiation such as cosmic rays of solar flares is a typical example of an environmental effect that can cause errors in a design. Known as latch-up, it is a type of short circuit that could have serious consequences in mission- or safety-critical applications. As chips become larger, the greater the chance of a latch-up. Smaller process geometries also increase the possibility of latch-up. Although random faults have always existed, a consumer usually lives with them, such as a minor device misbehaviour. A mobile phone not responding is typically remedied by switching off and on. However, in a safety-critical application, this is not possible - there’s no scope for things not working properly or the user finding a make-shift fix. Traditional techniques are aimed at finding systematic faults but not faults that might exist in the design. Tools that find random faults should be integrated into design flows. The random effect can never be removed so the design’s architecture must incorporate ways of detecting a fault when it occurs. Regression management tool An interesting technique that we have developed at Sondrel is a regression management tool (see Figure), designed to control regression suites and only run scenarios if previous, related checks have run and passed first. The tool generates detailed reports and ensures high-quality verification with less manual work. For designers, not only they must do everything properly but must prove it with detailed auditing and tracking, an increasingly important aspect in standards compliance and when handling larger designs. A small change or error can have a significant effect later on, hence by having detailed records, problems can easily be identified and corrected. Gone are the days when one person could hold an entire design in their minds: verification, auditing and tracking enables it to be spread safely between the many minds now needed for designs.