Leti, a research institute at CEA Tech, has made a breakthrough in six 3D-sequential-integration process, making it more reliable, better performing, easier to manufacture and cheaper. CoolCube, CEA-Leti’s 3D monolithic or 3D sequential CMOS technology allows several layers of devices to be vertically stacked with unique connecting-via density above tens-of-million/mm2. The technology, part of the “More thanMoore” technologies roster, halves the die area whilst showing a 26% gain in power. In addition, more improvements have been made, including processing the top layer in a front end of line (FEOL) environment with a restricted thermal budget. CEA-Leti’s recent 3D sequential integration breakthroughs include low-resistance poly-Si gate for the top field-effect transistors (FETs); full LT RSD (low temperature raised source and drain) epitaxy, including surface preparation; stable bonding above ultra-low k (ULK); stability of intermediate back end of line (iBEOL) between tiers with standard ULK/Cu technology; efficient contamination containment for wafers with Cu/ULK iBEOL, enabling their re-introduction in FEOL for top FET processing; and its Smart Cut process above a CMOS wafer. To obtain high-performance top FETs, low gate access resistance was achieved using UV nano-second laser recrystallisation of in-situ doped amorphous silicon. Full 500°C selective silicon-epitaxy process was demonstrated with an advanced LT surface preparation and a combination of dry and wet etch preparation. Epitaxial growth was demonstrated with the cyclic use of a new silicon precursor and dichlorine Cl2 etching. At the same time, the project paved the way to manufacturability of 3D sequential integration including iBEOL with standard ULK and Cu-metal lines. A bevel-edge contamination containment strategy comprised of three steps (bevel etch, decontamination and encapsulation) enabled reintroducing wafers in an FEOL environment following the BEOL process. In addition, the project also demonstrated for the first time the stability of line-to-line breakdown voltage for interconnections submitted to 500°C. The work also demonstrated a Smart Cut transfer of a crystalline silicon layer on a processed bottom level of FD-SOI CMOS devices, as an alternative to the SOI bonding-and-etch back process scheme for top channel fabrication.