August 2, 2012

Analog Devices (ADI) introduced a fully-programmable, jitter-attenuating, dual-clock translator IC (integrated circuit) to address the timing requirements of high-speed optical transport network (OTN) applications and high-density line cards. The AD9559 quad-input multiservice line card adaptive clock translator simultaneously supports different standard frequencies for wired communications applications, including synchronous Ethernet, SONET/SDH, 1/10/100G Ethernet, Fiber Channel, and other applications that require low jitter, flexibility and fast time-to-market. The AD9559 translator IC synchronously converts any standard input frequency to any standard output frequency at up to 1.25 GHz with sub-400-fs RMS (root mean square) total jitter over a 12-kHz to 20-MHz integration bandwidth. The AD9559 replaces two synchronous timing devices with a single IC, helping designers with board space constraints and cost optimisation. The AD9559 is the industry’s most flexible high-performance dual adaptive clock translation solution for high-density line cards and OTN applications. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency at the output to be dynamically adjusted over a ± 100 ppm range, around the nominal output frequency, with a resolution in frequency step as low as sub-0.1 ppb, without breaking the loop and reprogramming the part. The AD9559 IC’s parallel DPLL architecture allows the user to generate output clocks that are completely independent of each other. Each of the two DPLLs can be synchronised to one of up to four input references, and each DPLL generates two output clocks. The DPLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9559 continuously generates a clean (low jitter) valid output clock, even when all references have failed, by means of a digitally-controlled loop and holdover circuitry. The built-in programmability of the AD9559 clock translator allows network line card designers to use the same component in many different board designs, limiting the number of components needed and reducing overall system cost. At 10 mm x 10 mm in size, the AD9559 clock translator provides a compact, frequency agile, cost effective clock for line card designers. Applications include data communications, next-generation wired networking applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers. Key Features of the AD9559 Quad-input Dual Adaptive Clock Translator Dual DPLL architecture, with four reference inputs (single-ended or differential) going to an input crosspointSupports adaptive clocking and gapped clock input reference for OTN de-mapping applicationsSupports GR-1244 Stratum 3 stability in holdover modeSmooth reference switchover with virtually no disturbance on output phase.Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 SystemsSupports ITU-T G.8262 Synchronous Ethernet slave clocksSupports ITU-T G.823, G.824, G.825, and G.8261 Download data sheets and order samples: http://www.analog.com/AD9559For the single-channel version of this device, visit http://www.analog.com/AD9557

August 2, 2012

PRQA upgrades QA•C with enhanced dataflow capability and increased MISRA enforcement

Dual Adaptive Clock Translator Supports Wide Range of Wired Network Applications

PRQA upgrades QA•C with enhanced dataflow capability and increased MISRA enforcement

Dual Adaptive Clock Translator Supports Wide Range of Wired Network Applications

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