By Atsushi Kawamoto (Design Manager), Jesper Steensgaard (Staff Scientist), and Heemin Yang (Design Section Leader) – Linear Technology Corporation
The proliferation of complex, high performance system-on-chip integrated circuits has placed great demands on the automatic test equipment (ATE) systems used to manufacture them. Many ATE systems require measurement of critical parameters with extreme accuracy, as they must be significantly more accurate than the devices they are used to test. Modern ATE systems push the boundaries of state-of-the-art signal processing and require parts-permillion (ppm) accuracy. The design of such systems is highly sophisticated, requiring the highest performance integrated circuit components.
At the core of many precision ATE systems is an analogto-digital converter (ADC). The ADC plays a pivotal role, translating signals from the analog domain to digital for digital signal processing. The accuracy and performance of the ADC often defines the accuracy and performance of the overall system. Now a breakthrough in data conversion performance enables a new generation of higher accuracy lower-cost ATE systems.
Precision ATE System Requirements
Precision ATE systems require high-resolution ADCs to digitize real-world analog signals. Excellent DC specifications (such as offset, gain, and linearity) are typically required for the analog signal chain, including the ADC and supporting signal-conditioning circuitry (such as amplifiers, filters, and references).
In order to achieve ppm-level resolution and accuracy, many precision ATE systems are digitally calibrated to null out any system-level offset and gain errors. As a result, system accuracy is often limited by errors that cannot be suppressed by infrequent calibration, and system designers may be more concerned with potential drift of key parameters than they are with their static values. For example, precision ATE systems may require not only ppm-level accuracy at a fixed temperature, but also sub-ppm/C drift accuracy over a wide operating temperature range. ADC linearity is of critical concern for overall system accuracy.
ADC linearity is determined by complex interactions between the analog input signal and the ADC’s internal design and architecture. ADC nonlinearity errors are extremely di̇cult to calibrate at the system level, since such errors vary substantially from one digital code to another, and because they may be a strong function of temperature. ADC linearity and stability over temperature are crucial for the overall accuracy of precision ATE systems.
To meet these design challenges, a new family of 20-bit SAR ADCs provides an unprecedented level of performance and accuracy, simplifying the design of high-precision ATE systems. The LTC2378-20 from Linear Technology is the Àagship product in a family of pin- and software-compatible SAR ADCs featuring up to 20-bit no-missing-codes resolution and up to 104dB SNR at sample rates from 250ksps to 2Msps. The DC precision of this device is particularly impressive: the ADC integral nonlinearity (INL) errors are typically less than 0.5ppm, and are guaranteed to be less than 2ppm, for all codes over the entire operating temperature range from -40C to +85C. The offset error is 13ppm (maximum) with 0.007ppm/C drift, and the gain error is 10ppm with 0.05ppm/C drift. This extreme level of performance is achieved while operating at very low power, from 5.3mW at 250.sps to 21mW at 1Msps. Each device is available in small MSOP- 16 and DFN-16 packages.
Characteristics of SAR ADCs
SAR ADCs are characterized by their ability to acquire a precise snapshot in time of an analog input signal and to complete an analog-to-digital conversion operation within a single clock cycle. SAR ADCs excel at asynchronous “start-andgo” operations, and they are easy to use because the conversion result is available immediately within the same clock cycle. The ability to produce accurate conversion results with no cycle latency, even after long idle periods, makes SAR ADCs ideal for many precision ATE systems. Other types of ADCs, such as delta-sigma and pipelined ADCs require multiple clock cycles to complete a single conversion.
The guaranteed ppm-level linearity and accuracy of the LTC2378-20 is a game changer for many precision ATE systems. The device has been designed using a proprietary architecture that ensures linearity and minimizes its sensitivity to changes in temperature and other operating conditions. As a result, an unprecedented 2ppm INL specification is guaranteed over the entire operating temperature range.
The SAR ADC algorithm is based on a binary-search principle. The analog input is sampled onto a capacitor and is compared sequentially to fractions of a reference voltage selected by the SAR algorithm. The SAR ADC comprises three critical components: a capacitor-based digital-to-analog converter (CDAC), a fast low-noise comparator circuit, and a successiveapproximation register. The INL performance of a conventional SAR ADC may be limited by finite matching accuracy of individual capacitors in the CDAC, and many precision SAR ADCs employ analog or digital trimming techniques to improve the matching accuracy. However, as temperature varies and package and board stress is applied, CDAC capacitor matching invariably degrades and may limit the ADC’s linearity.
The LTC2378-20 achieves its state-of-the-art INL performance by implementing a proprietary architecture that makes the INL independent of CDAC capacitor mismatch. This makes the device exceptionally robust to the type of temperature variations and package stress effects that are present in harsh industrial environments. Furthermore, the comparator circuit is designed carefully to balance speed, power, and noise, such that the LTC2378-20 achieves an unprecedented 104dB signal-to-noise ratio (SNR), consuming only 21mW at 1Msps without introducing any cycle latency. The power consumption of the LTC2378-20 family of SAR ADCs is proportional to the sampling rate, so that they consume only microwatts when operated at 1ksps.
Accuracy and Speed
The LTC2378-20 achieves a level of accuracy previously available only with much slower ADC architectures, such as delta-sigma or multi-slope ADCs. High-channel-count ATE systems often employ such slow ADC architectures for precision DC measurements, with multiplexers allowing a single meter to service many inputs. The ADC conversion time can often be adjusted over a wide range to trade speed for resolution. However, measurement resolution is often limited to less than 16 bits at sample rates above 100ksps. The ADC device can take a million readings per second, with 2.3ppm noise resolution (standard deviation of noise, 104 dB SNR) of each reading. Results from multiple readings of the same analog signal may be combined digitally to improve the noise resolution, yielding performance exceeding that of multi-slope ADCs. For example, by averaging blocks of 10 samples, the LTC2378-20 effectively operates at 1Msps/10 100ksps with a 0.7ppm noise resolution (114dB SNR).
Delta-sigma and multi-slope ADCs may be configured to average an input signal during an observation/integration period to suppress noise and interference. An observation period of 100ms is often used to simultaneously suppress 50Hz and 60Hz line-frequency interference, resulting in a throughput of only 10 samples per second. Accordingly, it takes a full second to service 10 multiplexed channels with one multi-slope ADC. Figure 1 shows a single LTC2378-20 ADC operating at 102.4ksps, configured with a multiplexer circuit to simultaneously measure all 10 signals (interleaved) during the 100ms observation period. While preserving the suppression of line-frequency interference corresponding to the 100ms observation period, the throughput is increased by the factor of multiplexing (here 10, but can be higher), resulting in much higher productivity of the ATE system. In this example, the noise resolution is increased by averaging across 1024 samples taken from each channel during the observation period, providing 22 bits of noise resolution (0.07ppm or 70nV, rms). The averaging operation can be performed with a simple adder that is easy to implement in either programmable logic or in a processor. Thus, the LTC2378-20 enables significant increases in measurement speed, while maintaining the key advantages of prior architectures.
Because a single LTC2378-20 device can potentially replace several discrete components required for a multislope design, a valuable degree of design freedom opens up for balancing cost, board space, and channel count. Replacing a multiplexed meter with one or more LTC2378-20 ADCs can shrink system size, lower power, reduce solution cost, and increase speed by orders of magnitude over traditional approaches. Furthermore, because the device can operate in its native mode as a Nyquist ADC at up to 1Msps, a single LTC2378-20 ADC is ideal for use in systems that otherwise would require more than one type of ADC, such as a multislope ADC for high-accuracy low-noise measurements and a SAR ADC for faster lower-resolution measurements.
Precision ATE system designs have a new choice to improve signal chain performance. The 20-bit SAR ADC, LTC2378-20 provides an unprecedented level of accuracy (INL guaranteed at 2ppm) and low noise (104dB SNR) at a high conversion rate (1Msps) and low power consumption (21mW). The combination of high accuracy, low noise, and no-cycle latency makes LTC2378-20 highly versatile for use in precision measurements and control systems, enabling a new generation of highly accurate, Flexible and cost-effective precision ATE systems.
Linear Technology (UK) Ltd
Tel: 01628 477066