02 November 2010
Synopsys announced plans to expand test technology embedded in Synopsys’ RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis while simultaneously minimising the impact on design goals and project schedules. Design teams currently using Synopsys’ RTL synthesis and test solution are able to quickly implement compression to lower digital logic test costs, handle pin-limited test methodologies and execute on-chip testing of high speed blocks like USB and PCI Express cores.
Commencing today and continuing over the next twelve months, Synopsys is rolling out expanded synthesis-based test technology to provide defect coverage of embedded memories, lower test cost significantly with higher compression for pin-limited test and extremely large designs, and enable designers to rapidly analyse defective silicon devices. As with Synopsys’ widely-deployed DFTMAX(tm) compression, the new test technology will enable designers to achieve optimal quality-of-results and eliminate time consuming iterations between design and test.
“Our ongoing collaboration with Synopsys has produced several widely adopted, leading-edge test technologies such as managing power of the device on the tester and high defect coverage using a limited number of pins,” said Roberto Mattiuzzo, Design For Excellence manager in Technology R&D - Central CAD and Design Solutions at STMicroelectronics. “We continue to work together on more technology embedded in synthesis to further increase our test quality, control test costs and allow us to quickly analyse defective silicon under very tight schedules.”
“Synopsys delivers test technology that keeps pace with our evolving requirements,” said Bruce Fishbein, director of engineering at Cavium Networks. “As our designs become larger and more complex, test technology based on synthesis for defect coverage of digital logic will allow our designers to be more productive and continue to deliver high quality silicon on time.”
Testing complex chips requires embedding dedicated test logic throughout the entire design. Implementing this test logic outside the synthesis flow adversely impacts design characteristics such as performance and power consumption, leading to iterations between synthesis and test that lengthen project schedules. In contrast, Synopsys’ solution implements test within RTL synthesis to minimise the impact on design power, timing and area, accelerating convergence on both design and test goals. Synopsys is expanding this synthesis-based test technology to further increase designer productivity, improve quality and lower cost across all areas of manufacturing test and yield analysis, including the following:
Memory test and repair – In widespread use today, the DesignWare(tm) STAR Memory System delivers high coverage test and repair of embedded memories. Synopsys plans tighter integration with synthesis-based test to ensure fast turnaround time and maximum scalability.
Higher compression – To accommodate the need for even lower test cost for pin-limited methodologies as well as extremely large designs, Synopsys will provide higher compression utilising synthesis-based technology to maximise designer productivity.
Faster yield analysis – New integration between TetraMAX(r) ATPG and Yield Explorer yield analysis will enable designers to rapidly debug defective parts from a relatively small number of wafers.
“Our customers constantly need to shorten their schedules and improve throughput for all aspects of design and test,” said Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group. “To address this need, we are expanding our synthesis-based test technology to further increase the productivity gains, test quality and test cost savings designers achieve with Synopsys’ solution.”
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